Commit 7248f578 authored by Michal Simek's avatar Michal Simek
Browse files

arm64: zynqmp: Wire DP and DPDMA for dc1/dc4

parent 69f8aec4
Loading
Loading
Loading
Loading
+8 −0
Original line number Diff line number Diff line
@@ -391,3 +391,11 @@ &usb0 {
	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
	maximum-speed = "super-speed";
};

&zynqmp_dpdma {
	status = "okay";
};

&zynqmp_dpsub {
	status = "okay";
};
+9 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@
/*
 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
 *
 * (C) Copyright 2015 - 2019, Xilinx, Inc.
 * (C) Copyright 2015 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */
@@ -176,3 +176,11 @@ &uart1 {
&watchdog0 {
	status = "okay";
};

&zynqmp_dpdma {
	status = "okay";
};

&zynqmp_dpsub {
	status = "okay";
};