Commit 701a6a41 authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Mauro Carvalho Chehab
Browse files

media: hantro/cedrus: Remove unneeded slice size and slice offset 



The MPEG2_SLICE_PARAMS control is designed to refer to a
single slice. However, the Hantro and Cedrus drivers operate
in per-frame mode, and so does the current Ffmpeg and GStreamer
implementations that are tested with these two drivers.

In other words, the drivers are expecting all the slices in a picture
(with either frame or field structure) to be contained in
the OUTPUT buffer, which means the slice size and offset shouldn't be used.

Signed-off-by: default avatarEzequiel Garcia <ezequiel@collabora.com>
Tested-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Tested-by: default avatarDaniel Almeida <daniel.almeida@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent b6d7e803

drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c

+2 −2
Original line number Diff line number Diff line
@@ -203,7 +203,7 @@ void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx) 
	      G1_REG_TOPFIELDFIRST_E(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST);

	vdpu_write_relaxed(vpu, reg, G1_SWREG(4));



	reg = G1_REG_STRM_START_BIT(slice_params->data_bit_offset) |

	reg = G1_REG_STRM_START_BIT(0) |

	      G1_REG_QSCALE_TYPE(pic->flags & V4L2_MPEG2_PIC_FLAG_Q_SCALE_TYPE) |

	      G1_REG_CON_MV_E(pic->flags & V4L2_MPEG2_PIC_FLAG_CONCEALMENT_MV) |

	      G1_REG_INTRA_DC_PREC(pic->intra_dc_precision) |
@@ -212,7 +212,7 @@ void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx) 
	vdpu_write_relaxed(vpu, reg, G1_SWREG(5));



	reg = G1_REG_INIT_QP(1) |

	      G1_REG_STREAM_LEN(slice_params->bit_size >> 3);

	      G1_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));

	vdpu_write_relaxed(vpu, reg, G1_SWREG(6));



	reg = G1_REG_ALT_SCAN_FLAG_E(pic->flags & V4L2_MPEG2_PIC_FLAG_ALT_SCAN) |

drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c

+2 −2
Original line number Diff line number Diff line
@@ -177,7 +177,7 @@ void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx) 
	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));



	reg = VDPU_REG_INIT_QP(1) |

	      VDPU_REG_STREAM_LEN(slice_params->bit_size >> 3);

	      VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));

	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));



	reg = VDPU_REG_APF_THRESHOLD(8) |
@@ -220,7 +220,7 @@ void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx) 
	      VDPU_REG_TOPFIELDFIRST_E(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST);

	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));



	reg = VDPU_REG_STRM_START_BIT(slice_params->data_bit_offset) |

	reg = VDPU_REG_STRM_START_BIT(0) |

	      VDPU_REG_QSCALE_TYPE(pic->flags & V4L2_MPEG2_PIC_FLAG_Q_SCALE_TYPE) |

	      VDPU_REG_CON_MV_E(pic->flags & V4L2_MPEG2_PIC_FLAG_CONCEALMENT_MV) |

	      VDPU_REG_INTRA_DC_PREC(pic->intra_dc_precision) |

drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c

+3 −4
Original line number Diff line number Diff line
@@ -152,10 +152,9 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) 


	/* Source offset and length in bits. */



	cedrus_write(dev, VE_DEC_MPEG_VLD_OFFSET,

		     slice_params->data_bit_offset);

	cedrus_write(dev, VE_DEC_MPEG_VLD_OFFSET, 0);



	reg = slice_params->bit_size - slice_params->data_bit_offset;

	reg = vb2_get_plane_payload(&run->src->vb2_buf, 0) * 8;

	cedrus_write(dev, VE_DEC_MPEG_VLD_LEN, reg);



	/* Source beginning and end addresses. */
@@ -169,7 +168,7 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) 


	cedrus_write(dev, VE_DEC_MPEG_VLD_ADDR, reg);



	reg = src_buf_addr + DIV_ROUND_UP(slice_params->bit_size, 8);

	reg = src_buf_addr + vb2_get_plane_payload(&run->src->vb2_buf, 0);

	cedrus_write(dev, VE_DEC_MPEG_VLD_END_ADDR, reg);



	/* Macroblock address: start at the beginning. */