Loading drivers/clk/imx/clk-imx27.c +13 −0 Original line number Diff line number Diff line Loading @@ -47,6 +47,17 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; static struct clk *clk[IMX27_CLK_MAX]; static struct clk_onecell_data clk_data; static struct clk ** const uart_clks[] __initconst = { &clk[IMX27_CLK_PER1_GATE], &clk[IMX27_CLK_UART1_IPG_GATE], &clk[IMX27_CLK_UART2_IPG_GATE], &clk[IMX27_CLK_UART3_IPG_GATE], &clk[IMX27_CLK_UART4_IPG_GATE], &clk[IMX27_CLK_UART5_IPG_GATE], &clk[IMX27_CLK_UART6_IPG_GATE], NULL }; static void __init _mx27_clocks_init(unsigned long fref) { BUG_ON(!ccm); Loading Loading @@ -163,6 +174,8 @@ static void __init _mx27_clocks_init(unsigned long fref) clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); imx_register_uart_clocks(uart_clks); imx_print_silicon_rev("i.MX27", mx27_revision()); } Loading Loading
drivers/clk/imx/clk-imx27.c +13 −0 Original line number Diff line number Diff line Loading @@ -47,6 +47,17 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; static struct clk *clk[IMX27_CLK_MAX]; static struct clk_onecell_data clk_data; static struct clk ** const uart_clks[] __initconst = { &clk[IMX27_CLK_PER1_GATE], &clk[IMX27_CLK_UART1_IPG_GATE], &clk[IMX27_CLK_UART2_IPG_GATE], &clk[IMX27_CLK_UART3_IPG_GATE], &clk[IMX27_CLK_UART4_IPG_GATE], &clk[IMX27_CLK_UART5_IPG_GATE], &clk[IMX27_CLK_UART6_IPG_GATE], NULL }; static void __init _mx27_clocks_init(unsigned long fref) { BUG_ON(!ccm); Loading Loading @@ -163,6 +174,8 @@ static void __init _mx27_clocks_init(unsigned long fref) clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); imx_register_uart_clocks(uart_clks); imx_print_silicon_rev("i.MX27", mx27_revision()); } Loading