Commit 6e290323 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

x86/cpu: Move cpu_l[l2]c_id into topology info 



The topology IDs which identify the LLC and L2 domains clearly belong to
the per CPU topology information.

Move them into cpuinfo_x86::cpuinfo_topo and get rid of the extra per CPU
data and the related exports.

This also paves the way to do proper topology evaluation during early boot
because it removes the only per CPU dependency for that.

No functional change.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Tested-by: default avatarJuergen Gross <jgross@suse.com>
Tested-by: default avatarSohil Mehta <sohil.mehta@intel.com>
Tested-by: default avatarMichael Kelley <mikelley@microsoft.com>
Tested-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: default avatarZhang Rui <rui.zhang@intel.com>
Reviewed-by: default avatarArjan van de Ven <arjan@linux.intel.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230814085112.803864641@linutronix.de
parent 22dc9631

Documentation/arch/x86/topology.rst

+1 −3
Original line number Diff line number Diff line
@@ -79,9 +79,7 @@ Package-related topology information in the kernel: 
    The maximum possible number of packages in the system. Helpful for per

    package facilities to preallocate per package information.



  - cpu_llc_id:



    A per-CPU variable containing:

  - cpuinfo_x86.topo.llc_id:



      - On Intel, the first APIC ID of the list of CPUs sharing the Last Level

        Cache

arch/x86/events/amd/uncore.c

+1 −1
Original line number Diff line number Diff line
@@ -537,7 +537,7 @@ static int amd_uncore_cpu_starting(unsigned int cpu) 


	if (amd_uncore_llc) {

		uncore = *per_cpu_ptr(amd_uncore_llc, cpu);

		uncore->id = get_llc_id(cpu);

		uncore->id = per_cpu_llc_id(cpu);



		uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc);

		*per_cpu_ptr(amd_uncore_llc, cpu) = uncore;

arch/x86/include/asm/cacheinfo.h

+0 −3
Original line number Diff line number Diff line
@@ -7,9 +7,6 @@ extern unsigned int memory_caching_control; 
#define CACHE_MTRR 0x01

#define CACHE_PAT  0x02



void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu);

void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu);



void cache_disable(void);

void cache_enable(void);

void set_cache_aps_delayed_init(bool val);

arch/x86/include/asm/processor.h

+13 −1
Original line number Diff line number Diff line
@@ -99,6 +99,10 @@ struct cpuinfo_topology { 
	// Logical ID mappings

	u32			logical_pkg_id;

	u32			logical_die_id;



	// Cache level topology IDs

	u32			llc_id;

	u32			l2c_id;

};



struct cpuinfo_x86 {
@@ -689,7 +693,15 @@ extern int set_tsc_mode(unsigned int val); 


DECLARE_PER_CPU(u64, msr_misc_features_shadow);



extern u16 get_llc_id(unsigned int cpu);

static inline u16 per_cpu_llc_id(unsigned int cpu)

{

	return per_cpu(cpu_info.topo.llc_id, cpu);

}



static inline u16 per_cpu_l2c_id(unsigned int cpu)

{

	return per_cpu(cpu_info.topo.l2c_id, cpu);

}



#ifdef CONFIG_CPU_SUP_AMD

extern u32 amd_get_nodes_per_socket(void);

arch/x86/include/asm/smp.h

+0 −2
Original line number Diff line number Diff line
@@ -17,8 +17,6 @@ DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 
/* cpus sharing the last level cache: */

DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);

DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_l2c_shared_map);

DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id);

DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id);



DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid);

DECLARE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid);