Commit 6e18c9b3 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Block subvp if center timing is in use 



[Description]
- FW scheduling algorithm doesn't take into account of it's
  a center timing
- This affects where the subvp mclk switch can be scheduled
  (prevents HUBP vline interrupt from coming in if scheduled
  incorrectly)
- Block subvp center timing cases for now

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6b81090d

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h

+1 −0
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ bool dcn32_subvp_in_use(struct dc *dc, 
bool dcn32_mpo_in_use(struct dc_state *context);



bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);

bool dcn32_is_center_timing(struct pipe_ctx *pipe);



struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(

		struct dc_state *state,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c

+13 −0
Original line number Diff line number Diff line
@@ -255,6 +255,19 @@ bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context) 
	return false;

}



bool dcn32_is_center_timing(struct pipe_ctx *pipe)

{

	bool is_center_timing = false;



	if (pipe->stream) {

		if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||

				pipe->stream->timing.v_addressable != pipe->stream->src.height) {

			is_center_timing = true;

		}

	}

	return is_center_timing;

}



/**

 * *******************************************************************************************

 * dcn32_determine_det_override: Determine DET allocation for each pipe

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+1 −1
Original line number Diff line number Diff line
@@ -691,7 +691,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, 
		 *   to combine this with SubVP can cause issues with the scheduling).

		 * - Not TMZ surface

		 */

		if (pipe->plane_state && !pipe->top_pipe &&

		if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&

				pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&

				vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {

			while (pipe) {