Loading arch/arm/boot/dts/stm32h743-pinctrl.dtsi +11 −11 Original line number Diff line number Diff line Loading @@ -55,7 +55,7 @@ gpioa: gpio@58020000 { gpio-controller; #gpio-cells = <2>; reg = <0x0 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOA_CK>; st,bank-name = "GPIOA"; }; Loading @@ -63,7 +63,7 @@ gpiob: gpio@58020400 { gpio-controller; #gpio-cells = <2>; reg = <0x400 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOB_CK>; st,bank-name = "GPIOB"; }; Loading @@ -71,7 +71,7 @@ gpioc: gpio@58020800 { gpio-controller; #gpio-cells = <2>; reg = <0x800 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOC_CK>; st,bank-name = "GPIOC"; }; Loading @@ -79,7 +79,7 @@ gpiod: gpio@58020c00 { gpio-controller; #gpio-cells = <2>; reg = <0xc00 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOD_CK>; st,bank-name = "GPIOD"; }; Loading @@ -87,7 +87,7 @@ gpioe: gpio@58021000 { gpio-controller; #gpio-cells = <2>; reg = <0x1000 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOE_CK>; st,bank-name = "GPIOE"; }; Loading @@ -95,7 +95,7 @@ gpiof: gpio@58021400 { gpio-controller; #gpio-cells = <2>; reg = <0x1400 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOF_CK>; st,bank-name = "GPIOF"; }; Loading @@ -103,7 +103,7 @@ gpiog: gpio@58021800 { gpio-controller; #gpio-cells = <2>; reg = <0x1800 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOG_CK>; st,bank-name = "GPIOG"; }; Loading @@ -111,7 +111,7 @@ gpioh: gpio@58021c00 { gpio-controller; #gpio-cells = <2>; reg = <0x1c00 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOH_CK>; st,bank-name = "GPIOH"; }; Loading @@ -119,7 +119,7 @@ gpioi: gpio@58022000 { gpio-controller; #gpio-cells = <2>; reg = <0x2000 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOI_CK>; st,bank-name = "GPIOI"; }; Loading @@ -127,7 +127,7 @@ gpioj: gpio@58022400 { gpio-controller; #gpio-cells = <2>; reg = <0x2400 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOJ_CK>; st,bank-name = "GPIOJ"; }; Loading @@ -135,7 +135,7 @@ gpiok: gpio@58022800 { gpio-controller; #gpio-cells = <2>; reg = <0x2800 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOK_CK>; st,bank-name = "GPIOK"; }; Loading arch/arm/boot/dts/stm32h743.dtsi +39 −18 Original line number Diff line number Diff line Loading @@ -42,6 +42,8 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/clock/stm32h7-clks.h> #include <dt-bindings/mfd/stm32h7-rcc.h> / { clocks { Loading @@ -51,10 +53,16 @@ clk_hse: clk-hse { clock-frequency = <0>; }; timer_clk: timer-clk { clk_lse: clk-lse { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; clock-frequency = <32768>; }; clk_i2s: i2s_ckin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; }; Loading @@ -63,7 +71,7 @@ timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; clocks = <&timer_clk>; clocks = <&rcc TIM5_CK>; }; lptimer1: timer@40002400 { Loading @@ -71,7 +79,7 @@ lptimer1: timer@40002400 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x40002400 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM1_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -97,13 +105,13 @@ usart2: serial@40004400 { reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; clocks = <&timer_clk>; clocks = <&rcc USART2_CK>; }; dac: dac@40007400 { compatible = "st,stm32h7-dac-core"; reg = <0x40007400 0x400>; clocks = <&timer_clk>; clocks = <&rcc DAC12_CK>; clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; Loading @@ -129,8 +137,7 @@ usart1: serial@40011000 { reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; clocks = <&timer_clk>; clocks = <&rcc USART1_CK>; }; dma1: dma@40020000 { Loading @@ -144,7 +151,7 @@ dma1: dma@40020000 { <16>, <17>, <47>; clocks = <&timer_clk>; clocks = <&rcc DMA1_CK>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; Loading @@ -162,7 +169,7 @@ dma2: dma@40020400 { <68>, <69>, <70>; clocks = <&timer_clk>; clocks = <&rcc DMA2_CK>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; Loading @@ -176,14 +183,14 @@ dmamux1: dma-router@40020800 { dma-channels = <16>; dma-requests = <128>; dma-masters = <&dma1 &dma2>; clocks = <&timer_clk>; clocks = <&rcc DMA1_CK>; }; adc_12: adc@40022000 { compatible = "st,stm32h7-adc-core"; reg = <0x40022000 0x400>; interrupts = <18>; clocks = <&timer_clk>; clocks = <&rcc ADC12_CK>; clock-names = "bus"; interrupt-controller; #interrupt-cells = <1>; Loading Loading @@ -215,7 +222,7 @@ lptimer2: timer@58002400 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002400 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM2_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -241,7 +248,7 @@ lptimer3: timer@58002800 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002800 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM3_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -262,7 +269,7 @@ lptimer4: timer@58002c00 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002c00 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM4_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -277,7 +284,7 @@ lptimer5: timer@58003000 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58003000 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM5_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -290,17 +297,31 @@ pwm { vrefbuf: regulator@58003C00 { compatible = "st,stm32-vrefbuf"; reg = <0x58003C00 0x8>; clocks = <&timer_clk>; clocks = <&rcc VREF_CK>; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2500000>; status = "disabled"; }; rcc: reset-clock-controller@58024400 { compatible = "st,stm32h743-rcc", "st,stm32-rcc"; reg = <0x58024400 0x400>; #clock-cells = <1>; #reset-cells = <1>; clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; st,syscfg = <&pwrcfg>; }; pwrcfg: power-config@58024800 { compatible = "syscon"; reg = <0x58024800 0x400>; }; adc_3: adc@58026000 { compatible = "st,stm32h7-adc-core"; reg = <0x58026000 0x400>; interrupts = <127>; clocks = <&timer_clk>; clocks = <&rcc ADC3_CK>; clock-names = "bus"; interrupt-controller; #interrupt-cells = <1>; Loading Loading
arch/arm/boot/dts/stm32h743-pinctrl.dtsi +11 −11 Original line number Diff line number Diff line Loading @@ -55,7 +55,7 @@ gpioa: gpio@58020000 { gpio-controller; #gpio-cells = <2>; reg = <0x0 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOA_CK>; st,bank-name = "GPIOA"; }; Loading @@ -63,7 +63,7 @@ gpiob: gpio@58020400 { gpio-controller; #gpio-cells = <2>; reg = <0x400 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOB_CK>; st,bank-name = "GPIOB"; }; Loading @@ -71,7 +71,7 @@ gpioc: gpio@58020800 { gpio-controller; #gpio-cells = <2>; reg = <0x800 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOC_CK>; st,bank-name = "GPIOC"; }; Loading @@ -79,7 +79,7 @@ gpiod: gpio@58020c00 { gpio-controller; #gpio-cells = <2>; reg = <0xc00 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOD_CK>; st,bank-name = "GPIOD"; }; Loading @@ -87,7 +87,7 @@ gpioe: gpio@58021000 { gpio-controller; #gpio-cells = <2>; reg = <0x1000 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOE_CK>; st,bank-name = "GPIOE"; }; Loading @@ -95,7 +95,7 @@ gpiof: gpio@58021400 { gpio-controller; #gpio-cells = <2>; reg = <0x1400 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOF_CK>; st,bank-name = "GPIOF"; }; Loading @@ -103,7 +103,7 @@ gpiog: gpio@58021800 { gpio-controller; #gpio-cells = <2>; reg = <0x1800 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOG_CK>; st,bank-name = "GPIOG"; }; Loading @@ -111,7 +111,7 @@ gpioh: gpio@58021c00 { gpio-controller; #gpio-cells = <2>; reg = <0x1c00 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOH_CK>; st,bank-name = "GPIOH"; }; Loading @@ -119,7 +119,7 @@ gpioi: gpio@58022000 { gpio-controller; #gpio-cells = <2>; reg = <0x2000 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOI_CK>; st,bank-name = "GPIOI"; }; Loading @@ -127,7 +127,7 @@ gpioj: gpio@58022400 { gpio-controller; #gpio-cells = <2>; reg = <0x2400 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOJ_CK>; st,bank-name = "GPIOJ"; }; Loading @@ -135,7 +135,7 @@ gpiok: gpio@58022800 { gpio-controller; #gpio-cells = <2>; reg = <0x2800 0x400>; clocks = <&timer_clk>; clocks = <&rcc GPIOK_CK>; st,bank-name = "GPIOK"; }; Loading
arch/arm/boot/dts/stm32h743.dtsi +39 −18 Original line number Diff line number Diff line Loading @@ -42,6 +42,8 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/clock/stm32h7-clks.h> #include <dt-bindings/mfd/stm32h7-rcc.h> / { clocks { Loading @@ -51,10 +53,16 @@ clk_hse: clk-hse { clock-frequency = <0>; }; timer_clk: timer-clk { clk_lse: clk-lse { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; clock-frequency = <32768>; }; clk_i2s: i2s_ckin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; }; }; Loading @@ -63,7 +71,7 @@ timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; clocks = <&timer_clk>; clocks = <&rcc TIM5_CK>; }; lptimer1: timer@40002400 { Loading @@ -71,7 +79,7 @@ lptimer1: timer@40002400 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x40002400 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM1_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -97,13 +105,13 @@ usart2: serial@40004400 { reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; clocks = <&timer_clk>; clocks = <&rcc USART2_CK>; }; dac: dac@40007400 { compatible = "st,stm32h7-dac-core"; reg = <0x40007400 0x400>; clocks = <&timer_clk>; clocks = <&rcc DAC12_CK>; clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; Loading @@ -129,8 +137,7 @@ usart1: serial@40011000 { reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; clocks = <&timer_clk>; clocks = <&rcc USART1_CK>; }; dma1: dma@40020000 { Loading @@ -144,7 +151,7 @@ dma1: dma@40020000 { <16>, <17>, <47>; clocks = <&timer_clk>; clocks = <&rcc DMA1_CK>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; Loading @@ -162,7 +169,7 @@ dma2: dma@40020400 { <68>, <69>, <70>; clocks = <&timer_clk>; clocks = <&rcc DMA2_CK>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; Loading @@ -176,14 +183,14 @@ dmamux1: dma-router@40020800 { dma-channels = <16>; dma-requests = <128>; dma-masters = <&dma1 &dma2>; clocks = <&timer_clk>; clocks = <&rcc DMA1_CK>; }; adc_12: adc@40022000 { compatible = "st,stm32h7-adc-core"; reg = <0x40022000 0x400>; interrupts = <18>; clocks = <&timer_clk>; clocks = <&rcc ADC12_CK>; clock-names = "bus"; interrupt-controller; #interrupt-cells = <1>; Loading Loading @@ -215,7 +222,7 @@ lptimer2: timer@58002400 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002400 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM2_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -241,7 +248,7 @@ lptimer3: timer@58002800 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002800 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM3_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -262,7 +269,7 @@ lptimer4: timer@58002c00 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002c00 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM4_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -277,7 +284,7 @@ lptimer5: timer@58003000 { #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58003000 0x400>; clocks = <&timer_clk>; clocks = <&rcc LPTIM5_CK>; clock-names = "mux"; status = "disabled"; Loading @@ -290,17 +297,31 @@ pwm { vrefbuf: regulator@58003C00 { compatible = "st,stm32-vrefbuf"; reg = <0x58003C00 0x8>; clocks = <&timer_clk>; clocks = <&rcc VREF_CK>; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2500000>; status = "disabled"; }; rcc: reset-clock-controller@58024400 { compatible = "st,stm32h743-rcc", "st,stm32-rcc"; reg = <0x58024400 0x400>; #clock-cells = <1>; #reset-cells = <1>; clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; st,syscfg = <&pwrcfg>; }; pwrcfg: power-config@58024800 { compatible = "syscon"; reg = <0x58024800 0x400>; }; adc_3: adc@58026000 { compatible = "st,stm32h7-adc-core"; reg = <0x58026000 0x400>; interrupts = <127>; clocks = <&timer_clk>; clocks = <&rcc ADC3_CK>; clock-names = "bus"; interrupt-controller; #interrupt-cells = <1>; Loading