Commit 6d2fdb24 authored by Andreas Färber's avatar Andreas Färber
Browse files

arm64: dts: realtek: rtd129x: Introduce r-bus 



Model Realtek's register bus in DT.

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 690677c2

arch/arm64/boot/dts/realtek/rtd129x.dtsi

+72 −64
Original line number Diff line number Diff line
@@ -55,45 +55,52 @@ soc { 
		/* Exclude up to 2 GiB of RAM */

		ranges = <0x80000000 0x80000000 0x80000000>;



		reset1: reset-controller@98000000 {

		rbus: bus@98000000 {

			compatible = "simple-bus";

			reg = <0x98000000 0x200000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x98000000 0x200000>;



			reset1: reset-controller@0 {

				compatible = "snps,dw-low-reset";

			reg = <0x98000000 0x4>;

				reg = <0x0 0x4>;

				#reset-cells = <1>;

			};



		reset2: reset-controller@98000004 {

			reset2: reset-controller@4 {

				compatible = "snps,dw-low-reset";

			reg = <0x98000004 0x4>;

				reg = <0x4 0x4>;

				#reset-cells = <1>;

			};



		reset3: reset-controller@98000008 {

			reset3: reset-controller@8 {

				compatible = "snps,dw-low-reset";

			reg = <0x98000008 0x4>;

				reg = <0x8 0x4>;

				#reset-cells = <1>;

			};



		reset4: reset-controller@98000050 {

			reset4: reset-controller@50 {

				compatible = "snps,dw-low-reset";

			reg = <0x98000050 0x4>;

				reg = <0x50 0x4>;

				#reset-cells = <1>;

			};



		iso_reset: reset-controller@98007088 {

			iso_reset: reset-controller@7088 {

				compatible = "snps,dw-low-reset";

			reg = <0x98007088 0x4>;

				reg = <0x7088 0x4>;

				#reset-cells = <1>;

			};



		wdt: watchdog@98007680 {

			wdt: watchdog@7680 {

				compatible = "realtek,rtd1295-watchdog";

			reg = <0x98007680 0x100>;

				reg = <0x7680 0x100>;

				clocks = <&osc27M>;

			};



		uart0: serial@98007800 {

			uart0: serial@7800 {

				compatible = "snps,dw-apb-uart";

			reg = <0x98007800 0x400>;

				reg = <0x7800 0x400>;

				reg-shift = <2>;

				reg-io-width = <4>;

				clock-frequency = <27000000>;
@@ -101,9 +108,9 @@ uart0: serial@98007800 { 
				status = "disabled";

			};



		uart1: serial@9801b200 {

			uart1: serial@1b200 {

				compatible = "snps,dw-apb-uart";

			reg = <0x9801b200 0x100>;

				reg = <0x1b200 0x100>;

				reg-shift = <2>;

				reg-io-width = <4>;

				clock-frequency = <432000000>;
@@ -111,15 +118,16 @@ uart1: serial@9801b200 { 
				status = "disabled";

			};



		uart2: serial@9801b400 {

			uart2: serial@1b400 {

				compatible = "snps,dw-apb-uart";

			reg = <0x9801b400 0x100>;

				reg = <0x1b400 0x100>;

				reg-shift = <2>;

				reg-io-width = <4>;

				clock-frequency = <432000000>;

				resets = <&reset2 RTD1295_RSTN_UR2>;

				status = "disabled";

			};

		};



		gic: interrupt-controller@ff011000 {

			compatible = "arm,gic-400";