Commit 6ca11246 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: rename display clock block to dccg 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fab55d61

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1948,7 +1948,7 @@ void dc_resource_state_construct( 
		const struct dc *dc,

		struct dc_state *dst_ctx)

{

	dst_ctx->dis_clk = dc->res_pool->display_clock;

	dst_ctx->dis_clk = dc->res_pool->dccg;

}



enum dc_status dc_validate_global_state(

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+39 −39
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ 
#include "dal_asic_id.h"



#define TO_DCE_CLOCKS(clocks)\

	container_of(clocks, struct dce_disp_clk, base)

	container_of(clocks, struct dce_dccg, base)



#define REG(reg) \

	(clk_dce->regs->reg)
@@ -187,9 +187,9 @@ static int dce_divider_range_get_divider( 
	return div;

}



static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)

static int dce_clocks_get_dp_ref_freq(struct dccg *clk)

{

	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	int dprefclk_wdivider;

	int dprefclk_src_sel;

	int dp_ref_clk_khz = 600000;
@@ -250,9 +250,9 @@ static int dce_clocks_get_dp_ref_freq(struct display_clock *clk) 
 * or CLK0_CLK11 by SMU. For DCE120, it is wlays 600Mhz. Will re-visit

 * clock implementation

 */

static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk)

static int dce_clocks_get_dp_ref_freq_wrkaround(struct dccg *clk)

{

	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	int dp_ref_clk_khz = 600000;



	if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
@@ -274,10 +274,10 @@ static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk) 
	return dp_ref_clk_khz;

}

static enum dm_pp_clocks_state dce_get_required_clocks_state(

	struct display_clock *clk,

	struct dccg *clk,

	struct dc_clocks *req_clocks)

{

	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	int i;

	enum dm_pp_clocks_state low_req_clk;
@@ -306,10 +306,10 @@ static enum dm_pp_clocks_state dce_get_required_clocks_state( 
}



static int dce_set_clock(

	struct display_clock *clk,

	struct dccg *clk,

	int requested_clk_khz)

{

	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	struct bp_pixel_clock_parameters pxl_clk_params = { 0 };

	struct dc_bios *bp = clk->ctx->dc_bios;

	int actual_clock = requested_clk_khz;
@@ -341,10 +341,10 @@ static int dce_set_clock( 
}



static int dce_psr_set_clock(

	struct display_clock *clk,

	struct dccg *clk,

	int requested_clk_khz)

{

	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	struct dc_context *ctx = clk_dce->base.ctx;

	struct dc *core_dc = ctx->dc;

	struct dmcu *dmcu = core_dc->res_pool->dmcu;
@@ -357,10 +357,10 @@ static int dce_psr_set_clock( 
}



static int dce112_set_clock(

	struct display_clock *clk,

	struct dccg *clk,

	int requested_clk_khz)

{

	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);

	struct bp_set_dce_clock_parameters dce_clk_params;

	struct dc_bios *bp = clk->ctx->dc_bios;

	struct dc *core_dc = clk->ctx->dc;
@@ -409,7 +409,7 @@ static int dce112_set_clock( 
	return actual_clock;

}



static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)

static void dce_clock_read_integrated_info(struct dce_dccg *clk_dce)

{

	struct dc_debug *debug = &clk_dce->base.ctx->dc->debug;

	struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
@@ -467,7 +467,7 @@ static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce) 
			clk_dce->dfs_bypass_enabled = true;

}



static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)

static void dce_clock_read_ss_info(struct dce_dccg *clk_dce)

{

	struct dc_bios *bp = clk_dce->base.ctx->dc_bios;

	int ss_info_num = bp->funcs->get_ss_entry_number(
@@ -523,7 +523,7 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce) 
	}

}



static void dce12_update_clocks(struct display_clock *dccg,

static void dce12_update_clocks(struct dccg *dccg,

			struct dc_clocks *new_clocks,

			bool safe_to_lower)

{
@@ -549,7 +549,7 @@ static void dce12_update_clocks(struct display_clock *dccg, 
	}

}



static void dcn_update_clocks(struct display_clock *dccg,

static void dcn_update_clocks(struct dccg *dccg,

			struct dc_clocks *new_clocks,

			bool safe_to_lower)

{
@@ -628,7 +628,7 @@ static void dcn_update_clocks(struct display_clock *dccg, 
#endif

}



static void dce_update_clocks(struct display_clock *dccg,

static void dce_update_clocks(struct dccg *dccg,

			struct dc_clocks *new_clocks,

			bool safe_to_lower)

{
@@ -679,14 +679,14 @@ static const struct display_clock_funcs dce_funcs = { 
	.update_clocks = dce_update_clocks

};



static void dce_disp_clk_construct(

	struct dce_disp_clk *clk_dce,

static void dce_dccg_construct(

	struct dce_dccg *clk_dce,

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask)

{

	struct display_clock *base = &clk_dce->base;

	struct dccg *base = &clk_dce->base;



	base->ctx = ctx;

	base->funcs = &dce_funcs;
@@ -727,13 +727,13 @@ static void dce_disp_clk_construct( 
		DIVIDER_RANGE_MAX_DIVIDER_ID);

}



struct display_clock *dce_disp_clk_create(

struct dccg *dce_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask)

{

	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);

	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);



	if (clk_dce == NULL) {

		BREAK_TO_DEBUGGER();
@@ -744,19 +744,19 @@ struct display_clock *dce_disp_clk_create( 
		dce80_max_clks_by_state,

		sizeof(dce80_max_clks_by_state));



	dce_disp_clk_construct(

	dce_dccg_construct(

		clk_dce, ctx, regs, clk_shift, clk_mask);



	return &clk_dce->base;

}



struct display_clock *dce110_disp_clk_create(

struct dccg *dce110_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask)

{

	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);

	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);



	if (clk_dce == NULL) {

		BREAK_TO_DEBUGGER();
@@ -767,7 +767,7 @@ struct display_clock *dce110_disp_clk_create( 
		dce110_max_clks_by_state,

		sizeof(dce110_max_clks_by_state));



	dce_disp_clk_construct(

	dce_dccg_construct(

		clk_dce, ctx, regs, clk_shift, clk_mask);



	clk_dce->base.funcs = &dce110_funcs;
@@ -775,13 +775,13 @@ struct display_clock *dce110_disp_clk_create( 
	return &clk_dce->base;

}



struct display_clock *dce112_disp_clk_create(

struct dccg *dce112_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask)

{

	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);

	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);



	if (clk_dce == NULL) {

		BREAK_TO_DEBUGGER();
@@ -792,7 +792,7 @@ struct display_clock *dce112_disp_clk_create( 
		dce112_max_clks_by_state,

		sizeof(dce112_max_clks_by_state));



	dce_disp_clk_construct(

	dce_dccg_construct(

		clk_dce, ctx, regs, clk_shift, clk_mask);



	clk_dce->base.funcs = &dce112_funcs;
@@ -800,9 +800,9 @@ struct display_clock *dce112_disp_clk_create( 
	return &clk_dce->base;

}



struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)

struct dccg *dce120_dccg_create(struct dc_context *ctx)

{

	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);

	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);



	if (clk_dce == NULL) {

		BREAK_TO_DEBUGGER();
@@ -813,7 +813,7 @@ struct display_clock *dce120_disp_clk_create(struct dc_context *ctx) 
		dce120_max_clks_by_state,

		sizeof(dce120_max_clks_by_state));



	dce_disp_clk_construct(

	dce_dccg_construct(

		clk_dce, ctx, NULL, NULL, NULL);



	clk_dce->base.funcs = &dce120_funcs;
@@ -821,9 +821,9 @@ struct display_clock *dce120_disp_clk_create(struct dc_context *ctx) 
	return &clk_dce->base;

}



struct display_clock *dcn_disp_clk_create(struct dc_context *ctx)

struct dccg *dcn_dccg_create(struct dc_context *ctx)

{

	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);

	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);



	if (clk_dce == NULL) {

		BREAK_TO_DEBUGGER();
@@ -831,7 +831,7 @@ struct display_clock *dcn_disp_clk_create(struct dc_context *ctx) 
	}



	/* TODO strip out useful stuff out of dce constructor */

	dce_disp_clk_construct(

	dce_dccg_construct(

		clk_dce, ctx, NULL, NULL, NULL);



	clk_dce->base.funcs = &dcn_funcs;
@@ -839,10 +839,10 @@ struct display_clock *dcn_disp_clk_create(struct dc_context *ctx) 
	return &clk_dce->base;

}



void dce_disp_clk_destroy(struct display_clock **disp_clk)

void dce_dccg_destroy(struct dccg **dccg)

{

	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk);

	struct dce_dccg *clk_dce = TO_DCE_CLOCKS(*dccg);



	kfree(clk_dce);

	*disp_clk = NULL;

	*dccg = NULL;

}

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h

+8 −8
Original line number Diff line number Diff line
@@ -82,8 +82,8 @@ struct dce_divider_range { 
	int did_max;

};



struct dce_disp_clk {

	struct display_clock base;

struct dce_dccg {

	struct dccg base;

	const struct dce_disp_clk_registers *regs;

	const struct dce_disp_clk_shift *clk_shift;

	const struct dce_disp_clk_mask *clk_mask;
@@ -108,28 +108,28 @@ struct dce_disp_clk { 
};





struct display_clock *dce_disp_clk_create(

struct dccg *dce_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask);



struct display_clock *dce110_disp_clk_create(

struct dccg *dce110_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask);



struct display_clock *dce112_disp_clk_create(

struct dccg *dce112_dccg_create(

	struct dc_context *ctx,

	const struct dce_disp_clk_registers *regs,

	const struct dce_disp_clk_shift *clk_shift,

	const struct dce_disp_clk_mask *clk_mask);



struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);

struct dccg *dce120_dccg_create(struct dc_context *ctx);



struct display_clock *dcn_disp_clk_create(struct dc_context *ctx);

struct dccg *dcn_dccg_create(struct dc_context *ctx);



void dce_disp_clk_destroy(struct display_clock **disp_clk);

void dce_dccg_destroy(struct dccg **dccg);



#endif /* _DCE_CLOCKS_H_ */

drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

+2 −2
Original line number Diff line number Diff line
@@ -168,8 +168,8 @@ void dce100_set_bandwidth( 


	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);



	dc->res_pool->display_clock->funcs->update_clocks(

			dc->res_pool->display_clock,

	dc->res_pool->dccg->funcs->update_clocks(

			dc->res_pool->dccg,

			&req_clks,

			decrease_allowed);

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+5 −5
Original line number Diff line number Diff line
@@ -644,8 +644,8 @@ static void destruct(struct dce110_resource_pool *pool) 
			dce_aud_destroy(&pool->base.audios[i]);

	}



	if (pool->base.display_clock != NULL)

		dce_disp_clk_destroy(&pool->base.display_clock);

	if (pool->base.dccg != NULL)

		dce_dccg_destroy(&pool->base.dccg);



	if (pool->base.abm != NULL)

				dce_abm_destroy(&pool->base.abm);
@@ -817,11 +817,11 @@ static bool construct( 
		}

	}



	pool->base.display_clock = dce_disp_clk_create(ctx,

	pool->base.dccg = dce_dccg_create(ctx,

			&disp_clk_regs,

			&disp_clk_shift,

			&disp_clk_mask);

	if (pool->base.display_clock == NULL) {

	if (pool->base.dccg == NULL) {

		dm_error("DC: failed to create display clock!\n");

		BREAK_TO_DEBUGGER();

		goto res_create_fail;
@@ -851,7 +851,7 @@ static bool construct( 
	 * max_clock_state

	 */

	if (dm_pp_get_static_clocks(ctx, &static_clk_info))

		pool->base.display_clock->max_clks_state =

		pool->base.dccg->max_clks_state =

					static_clk_info.max_clocks_state;

	{

		struct irq_service_init_data init_data;