Commit 6c3550e9 authored by Thierry Reding's avatar Thierry Reding
Browse files

Merge branch 'for-5.10/dt-bindings' into for-5.10/arm/dt

parents 9123e3a7 e9b64103

Documentation/devicetree/bindings/arm/tegra.yaml

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@@ -119,3 +119,7 @@ properties: 
        items:

          - const: nvidia,p3509-0000+p3668-0000

          - const: nvidia,tegra194

      - items:

          - enum:

              - nvidia,tegra234-vdk

          - const: nvidia,tegra234

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt

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@@ -4,6 +4,7 @@ Required properties: 
- compatible: Should contain one of the following:

  - "nvidia,tegra186-pmc": for Tegra186

  - "nvidia,tegra194-pmc": for Tegra194

  - "nvidia,tegra234-pmc": for Tegra234

- reg: Must contain an (offset, length) pair of the register set for each

  entry in reg-names.

- reg-names: Must include the following entries:
@@ -11,7 +12,7 @@ Required properties: 
  - "wake"

  - "aotag"

  - "scratch"

  - "misc" (Only for Tegra194)

  - "misc" (Only for Tegra194 and later)



Optional properties:

- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.

Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt

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@@ -7,6 +7,7 @@ Required properties: 
  For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".

  For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain

  "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".

  For Tegra234 must contain "nvidia,tegra234-efuse".

  Details:

  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data

	due to a hardware bug. Tegra20 also lacks certain information which is

Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt

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NVIDIA Tegra186 MISC register block

NVIDIA Tegra186 (and later) MISC register block



The MISC register block found on Tegra186 SoCs contains registers that can be

used to identify a given chip and various strapping options.

The MISC register block found on Tegra186 and later SoCs contains registers

that can be used to identify a given chip and various strapping options.



Required properties:

- compatible: Must be:

  - Tegra186: "nvidia,tegra186-misc"

  - Tegra194: "nvidia,tegra194-misc"

  - Tegra234: "nvidia,tegra234-misc"

- reg: Should contain 2 entries: The first entry gives the physical address

       and length of the register region which contains revision and debug

       features. The second entry specifies the physical address and length

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block

NVIDIA Tegra APBMISC block



Required properties:

- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc".  For Tegra30,

  must be "nvidia,tegra30-apbmisc".  Otherwise, must contain

  "nvidia,<chip>-apbmisc", plus one of the above, where <chip> is tegra114,

  tegra124, tegra132.

- compatible: Must be:

  - Tegra20: "nvidia,tegra20-apbmisc"

  - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"

  - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"

  - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"

  - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"

  - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"

- reg: Should contain 2 entries: the first entry gives the physical address

       and length of the registers which contain revision and debug features.

       The second entry gives the physical address and length of the