Commit 6b55b1e2 authored by Tinghan Shen's avatar Tinghan Shen Committed by Mathieu Poirier
Browse files

dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP 



Extend the SCP binding to describe the MT8195 dual-core SCP.

Under different applications, the MT8195 SCP can be used as single-core
or dual-core. This change keeps the single-core definitions and
adds new definitions for the dual-core use case.

Signed-off-by: default avatarTinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230901080935.14571-4-tinghan.shen@mediatek.com


Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent cdd22187

Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml

+141 −4
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties: 
      - mediatek,mt8188-scp

      - mediatek,mt8192-scp

      - mediatek,mt8195-scp

      - mediatek,mt8195-scp-dual



  reg:

    description:
@@ -31,10 +32,7 @@ properties: 


  reg-names:

    minItems: 2

    items:

      - const: sram

      - const: cfg

      - const: l1tcm

    maxItems: 3



  clocks:

    description:
@@ -70,6 +68,81 @@ properties: 


    unevaluatedProperties: false



  '#address-cells':

    const: 1



  '#size-cells':

    const: 1



  ranges:

    description:

      Standard ranges definition providing address translations for

      local SCP SRAM address spaces to bus addresses.



patternProperties:

  "^scp@[a-f0-9]+$":

    type: object

    description:

      The MediaTek SCP integrated to SoC might be a multi-core version.

      The other cores are represented as child nodes of the boot core.

      There are some integration differences for the IP like the usage of

      address translator for translating SoC bus addresses into address space

      for the processor.



      Each SCP core has own cache memory. The SRAM and L1TCM are shared by

      cores. The power of cache, SRAM and L1TCM power should be enabled

      before booting SCP cores. The size of cache, SRAM, and L1TCM are varied

      on differnt SoCs.



      The SCP cores do not use an MMU, but has a set of registers to

      control the translations between 32-bit CPU addresses into system bus

      addresses. Cache and memory access settings are provided through a

      Memory Protection Unit (MPU), programmable only from the SCP.



    properties:

      compatible:

        enum:

          - mediatek,scp-core



      reg:

        description: The base address and size of SRAM.

        maxItems: 1



      reg-names:

        const: sram



      interrupts:

        maxItems: 1



      firmware-name:

        $ref: /schemas/types.yaml#/definitions/string

        description:

          If present, name (or relative path) of the file within the

          firmware search path containing the firmware image used when

          initializing sub cores of multi-core SCP.



      memory-region:

        maxItems: 1



      cros-ec-rpmsg:

        $ref: /schemas/mfd/google,cros-ec.yaml

        description:

          This subnode represents the rpmsg device. The properties

          of this node are defined by the individual bindings for

          the rpmsg devices.



        required:

          - mediatek,rpmsg-name



        unevaluatedProperties: false



    required:

      - compatible

      - reg

      - reg-names



    additionalProperties: false



required:

  - compatible

  - reg
@@ -99,7 +172,37 @@ allOf: 
        reg:

          maxItems: 2

        reg-names:

          items:

            - const: sram

            - const: cfg

  - if:

      properties:

        compatible:

          enum:

            - mediatek,mt8192-scp

            - mediatek,mt8195-scp

    then:

      properties:

        reg:

          maxItems: 3

        reg-names:

          items:

            - const: sram

            - const: cfg

            - const: l1tcm

  - if:

      properties:

        compatible:

          enum:

            - mediatek,mt8195-scp-dual

    then:

      properties:

        reg:

          maxItems: 2

        reg-names:

          items:

            - const: cfg

            - const: l1tcm



additionalProperties: false
@@ -121,3 +224,37 @@ examples: 
            mediatek,rpmsg-name = "cros-ec-rpmsg";

        };

    };



  - |

    scp@10500000 {

        compatible = "mediatek,mt8195-scp-dual";

        reg = <0x10720000 0xe0000>,

              <0x10700000 0x8000>;

        reg-names = "cfg", "l1tcm";



        #address-cells = <1>;

        #size-cells = <1>;

        ranges = <0 0x10500000 0x100000>;



        scp@0 {

            compatible = "mediatek,scp-core";

            reg = <0x0 0xa0000>;

            reg-names = "sram";



            cros-ec-rpmsg {

                compatible = "google,cros-ec-rpmsg";

                mediatek,rpmsg-name = "cros-ec-rpmsg";

            };

        };



        scp@a0000 {

            compatible = "mediatek,scp-core";

            reg = <0xa0000 0x20000>;

            reg-names = "sram";



            cros-ec-rpmsg {

                compatible = "google,cros-ec-rpmsg";

                mediatek,rpmsg-name = "cros-ec-rpmsg";

            };

        };

    };