Loading drivers/mtd/nand/raw/davinci_nand.c +1 −24 Original line number Diff line number Diff line Loading @@ -27,7 +27,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/mtd/rawnand.h> #include <linux/mtd/partitions.h> Loading Loading @@ -55,7 +54,6 @@ struct davinci_nand_info { struct nand_chip chip; struct device *dev; struct clk *clk; bool is_readmode; Loading Loading @@ -703,22 +701,6 @@ static int nand_davinci_probe(struct platform_device *pdev) /* Use board-specific ECC config */ info->chip.ecc.mode = pdata->ecc_mode; ret = -EINVAL; info->clk = devm_clk_get(&pdev->dev, "aemif"); if (IS_ERR(info->clk)) { ret = PTR_ERR(info->clk); dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); return ret; } ret = clk_prepare_enable(info->clk); if (ret < 0) { dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", ret); goto err_clk_enable; } spin_lock_irq(&davinci_nand_lock); /* put CSxNAND into NAND mode */ Loading @@ -732,7 +714,7 @@ static int nand_davinci_probe(struct platform_device *pdev) ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL); if (ret < 0) { dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); goto err; return ret; } switch (info->chip.ecc.mode) { Loading Loading @@ -838,9 +820,6 @@ static int nand_davinci_probe(struct platform_device *pdev) nand_cleanup(&info->chip); err: clk_disable_unprepare(info->clk); err_clk_enable: spin_lock_irq(&davinci_nand_lock); if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) ecc4_busy = false; Loading @@ -859,8 +838,6 @@ static int nand_davinci_remove(struct platform_device *pdev) nand_release(nand_to_mtd(&info->chip)); clk_disable_unprepare(info->clk); return 0; } Loading Loading
drivers/mtd/nand/raw/davinci_nand.c +1 −24 Original line number Diff line number Diff line Loading @@ -27,7 +27,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/mtd/rawnand.h> #include <linux/mtd/partitions.h> Loading Loading @@ -55,7 +54,6 @@ struct davinci_nand_info { struct nand_chip chip; struct device *dev; struct clk *clk; bool is_readmode; Loading Loading @@ -703,22 +701,6 @@ static int nand_davinci_probe(struct platform_device *pdev) /* Use board-specific ECC config */ info->chip.ecc.mode = pdata->ecc_mode; ret = -EINVAL; info->clk = devm_clk_get(&pdev->dev, "aemif"); if (IS_ERR(info->clk)) { ret = PTR_ERR(info->clk); dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); return ret; } ret = clk_prepare_enable(info->clk); if (ret < 0) { dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", ret); goto err_clk_enable; } spin_lock_irq(&davinci_nand_lock); /* put CSxNAND into NAND mode */ Loading @@ -732,7 +714,7 @@ static int nand_davinci_probe(struct platform_device *pdev) ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL); if (ret < 0) { dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); goto err; return ret; } switch (info->chip.ecc.mode) { Loading Loading @@ -838,9 +820,6 @@ static int nand_davinci_probe(struct platform_device *pdev) nand_cleanup(&info->chip); err: clk_disable_unprepare(info->clk); err_clk_enable: spin_lock_irq(&davinci_nand_lock); if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) ecc4_busy = false; Loading @@ -859,8 +838,6 @@ static int nand_davinci_remove(struct platform_device *pdev) nand_release(nand_to_mtd(&info->chip)); clk_disable_unprepare(info->clk); return 0; } Loading