Commit 667433c4 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Refresh haswellx metrics and events 

Update the haswellx metrics and events using the new tooling from:

  https://github.com/intel/perfmon



The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. The formatting
changes increase consistency across the json files.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-5-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 87493110

tools/perf/pmu-events/arch/x86/haswellx/cache.json

+0 −217

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tools/perf/pmu-events/arch/x86/haswellx/floating-point.json

+0 −20
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC6",

        "EventName": "AVX_INSTS.ALL",

        "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
@@ -11,8 +9,6 @@ 
    },

    {

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.ANY",
@@ -22,8 +18,6 @@ 
    },

    {

        "BriefDescription": "Number of SIMD FP assists due to input values",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -32,8 +26,6 @@ 
    },

    {

        "BriefDescription": "Number of SIMD FP assists due to Output values",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -42,8 +34,6 @@ 
    },

    {

        "BriefDescription": "Number of X87 assists due to input value.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_INPUT",

        "PublicDescription": "Number of X87 FP assists due to input values.",
@@ -52,8 +42,6 @@ 
    },

    {

        "BriefDescription": "Number of X87 assists due to output value.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "PublicDescription": "Number of X87 FP assists due to output values.",
@@ -62,8 +50,6 @@ 
    },

    {

        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x58",

        "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

        "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
@@ -72,8 +58,6 @@ 
    },

    {

        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x58",

        "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

        "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
@@ -82,8 +66,6 @@ 
    },

    {

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "Errata": "HSD56, HSM57",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -92,8 +74,6 @@ 
    },

    {

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "Errata": "HSD56, HSM57",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

tools/perf/pmu-events/arch/x86/haswellx/frontend.json

+0 −58
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.ANY",

        "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
@@ -11,8 +9,6 @@ 
    },

    {

        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xAB",

        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",

        "SampleAfterValue": "2000003",
@@ -20,8 +16,6 @@ 
    },

    {

        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.HIT",

        "SampleAfterValue": "2000003",
@@ -29,8 +23,6 @@ 
    },

    {

        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.IFDATA_STALL",

        "SampleAfterValue": "2000003",
@@ -38,8 +30,6 @@ 
    },

    {

        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.IFETCH_STALL",

        "SampleAfterValue": "2000003",
@@ -47,8 +37,6 @@ 
    },

    {

        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
@@ -57,8 +45,6 @@ 
    },

    {

        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "4",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -68,8 +54,6 @@ 
    },

    {

        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -79,8 +63,6 @@ 
    },

    {

        "BriefDescription": "Cycles MITE is delivering 4 Uops",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "4",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -90,8 +72,6 @@ 
    },

    {

        "BriefDescription": "Cycles MITE is delivering any Uop",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -101,8 +81,6 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.DSB_CYCLES",
@@ -111,8 +89,6 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",

        "EventName": "IDQ.DSB_UOPS",

        "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
@@ -121,8 +97,6 @@ 
    },

    {

        "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "Errata": "HSD135",

        "EventCode": "0x79",

        "EventName": "IDQ.EMPTY",
@@ -132,8 +106,6 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_ALL_UOPS",

        "PublicDescription": "Number of uops delivered to IDQ from any path.",
@@ -142,8 +114,6 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_CYCLES",
@@ -152,8 +122,6 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",

        "EventName": "IDQ.MITE_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
@@ -162,8 +130,6 @@ 
    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_CYCLES",
@@ -173,8 +139,6 @@ 
    },

    {

        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_CYCLES",
@@ -183,8 +147,6 @@ 
    },

    {

        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x79",
@@ -194,8 +156,6 @@ 
    },

    {

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
@@ -204,8 +164,6 @@ 
    },

    {

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_MITE_UOPS",

        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
@@ -214,8 +172,6 @@ 
    },

    {

        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x79",
@@ -225,8 +181,6 @@ 
    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_UOPS",

        "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",
@@ -235,8 +189,6 @@ 
    },

    {

        "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "Errata": "HSD135",

        "EventCode": "0x9C",

        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
@@ -246,8 +198,6 @@ 
    },

    {

        "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "4",

        "Errata": "HSD135",

        "EventCode": "0x9C",
@@ -258,8 +208,6 @@ 
    },

    {

        "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "1",

        "Errata": "HSD135",

        "EventCode": "0x9C",
@@ -270,8 +218,6 @@ 
    },

    {

        "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "3",

        "Errata": "HSD135",

        "EventCode": "0x9C",
@@ -281,8 +227,6 @@ 
    },

    {

        "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "2",

        "Errata": "HSD135",

        "EventCode": "0x9C",
@@ -292,8 +236,6 @@ 
    },

    {

        "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "1",

        "Errata": "HSD135",

        "EventCode": "0x9C",

tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json

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tools/perf/pmu-events/arch/x86/haswellx/memory.json

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