Loading arch/mips/bcm63xx/cpu.c +2 −2 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ const int *bcm63xx_irqs; EXPORT_SYMBOL(bcm63xx_irqs); static u16 bcm63xx_cpu_id; static u16 bcm63xx_cpu_rev; static u8 bcm63xx_cpu_rev; static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; Loading Loading @@ -87,7 +87,7 @@ u16 __bcm63xx_get_cpu_id(void) EXPORT_SYMBOL(__bcm63xx_get_cpu_id); u16 bcm63xx_get_cpu_rev(void) u8 bcm63xx_get_cpu_rev(void) { return bcm63xx_cpu_rev; } Loading arch/mips/bcm63xx/setup.c +1 −1 Original line number Diff line number Diff line Loading @@ -126,7 +126,7 @@ static void __bcm63xx_machine_reboot(char *p) const char *get_system_type(void) { static char buf[128]; snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)", snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%02X)", board_get_name(), bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev()); return buf; Loading arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +1 −1 Original line number Diff line number Diff line Loading @@ -18,7 +18,7 @@ void __init bcm63xx_cpu_init(void); u16 __bcm63xx_get_cpu_id(void); u16 bcm63xx_get_cpu_rev(void); u8 bcm63xx_get_cpu_rev(void); unsigned int bcm63xx_get_cpu_freq(void); #ifdef CONFIG_BCM63XX_CPU_6328 Loading arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +1 −1 Original line number Diff line number Diff line Loading @@ -10,7 +10,7 @@ #define REV_CHIPID_SHIFT 16 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) #define REV_REVID_SHIFT 0 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) /* Clock Control register */ #define PERF_CKCTL_REG 0x4 Loading Loading
arch/mips/bcm63xx/cpu.c +2 −2 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ const int *bcm63xx_irqs; EXPORT_SYMBOL(bcm63xx_irqs); static u16 bcm63xx_cpu_id; static u16 bcm63xx_cpu_rev; static u8 bcm63xx_cpu_rev; static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; Loading Loading @@ -87,7 +87,7 @@ u16 __bcm63xx_get_cpu_id(void) EXPORT_SYMBOL(__bcm63xx_get_cpu_id); u16 bcm63xx_get_cpu_rev(void) u8 bcm63xx_get_cpu_rev(void) { return bcm63xx_cpu_rev; } Loading
arch/mips/bcm63xx/setup.c +1 −1 Original line number Diff line number Diff line Loading @@ -126,7 +126,7 @@ static void __bcm63xx_machine_reboot(char *p) const char *get_system_type(void) { static char buf[128]; snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)", snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%02X)", board_get_name(), bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev()); return buf; Loading
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +1 −1 Original line number Diff line number Diff line Loading @@ -18,7 +18,7 @@ void __init bcm63xx_cpu_init(void); u16 __bcm63xx_get_cpu_id(void); u16 bcm63xx_get_cpu_rev(void); u8 bcm63xx_get_cpu_rev(void); unsigned int bcm63xx_get_cpu_freq(void); #ifdef CONFIG_BCM63XX_CPU_6328 Loading
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +1 −1 Original line number Diff line number Diff line Loading @@ -10,7 +10,7 @@ #define REV_CHIPID_SHIFT 16 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) #define REV_REVID_SHIFT 0 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) /* Clock Control register */ #define PERF_CKCTL_REG 0x4 Loading