Commit 652f2efa authored by Rob Herring's avatar Rob Herring
Browse files

dt-bindings: net: Convert MDIO mux bindings to DT schema 



Convert the common MDIO mux bindings to DT schema.

Drop the example from mdio-mux.yaml as mdio-mux-gpio.yaml has the same one.

Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: netdev@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20210526181411.2888516-1-robh@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent e9ab77a4

Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt

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@@ -17,7 +17,7 @@ Optional properties: 
- clocks: phandle of the core clock which drives the mdio block.



Additional information regarding generic multiplexer properties can be found

at- Documentation/devicetree/bindings/net/mdio-mux.txt

at- Documentation/devicetree/bindings/net/mdio-mux.yaml





for example:

Documentation/devicetree/bindings/net/mdio-mux-gpio.txt

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Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.



This is a special case of a MDIO bus multiplexer.  One or more GPIO

lines are used to control which child bus is connected.



Required properties in addition to the generic multiplexer properties:



- compatible : mdio-mux-gpio.

- gpios : GPIO specifiers for each GPIO line.  One or more must be specified.





Example :



	/* The parent MDIO bus. */

	smi1: mdio@1180000001900 {

		compatible = "cavium,octeon-3860-mdio";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x11800 0x00001900 0x0 0x40>;

	};



	/*

	   An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a

	   pair of GPIO lines.  Child busses 2 and 3 populated with 4

	   PHYs each.

	 */

	mdio-mux {

		compatible = "mdio-mux-gpio";

		gpios = <&gpio1 3 0>, <&gpio1 4 0>;

		mdio-parent-bus = <&smi1>;

		#address-cells = <1>;

		#size-cells = <0>;



		mdio@2 {

			reg = <2>;

			#address-cells = <1>;

			#size-cells = <0>;



			phy11: ethernet-phy@1 {

				reg = <1>;

				marvell,reg-init = <3 0x10 0 0x5777>,

					<3 0x11 0 0x00aa>,

					<3 0x12 0 0x4105>,

					<3 0x13 0 0x0a60>;

				interrupt-parent = <&gpio>;

				interrupts = <10 8>; /* Pin 10, active low */

			};

			phy12: ethernet-phy@2 {

				reg = <2>;

				marvell,reg-init = <3 0x10 0 0x5777>,

					<3 0x11 0 0x00aa>,

					<3 0x12 0 0x4105>,

					<3 0x13 0 0x0a60>;

				interrupt-parent = <&gpio>;

				interrupts = <10 8>; /* Pin 10, active low */

			};

			phy13: ethernet-phy@3 {

				reg = <3>;

				marvell,reg-init = <3 0x10 0 0x5777>,

					<3 0x11 0 0x00aa>,

					<3 0x12 0 0x4105>,

					<3 0x13 0 0x0a60>;

				interrupt-parent = <&gpio>;

				interrupts = <10 8>; /* Pin 10, active low */

			};

			phy14: ethernet-phy@4 {

				reg = <4>;

				marvell,reg-init = <3 0x10 0 0x5777>,

					<3 0x11 0 0x00aa>,

					<3 0x12 0 0x4105>,

					<3 0x13 0 0x0a60>;

				interrupt-parent = <&gpio>;

				interrupts = <10 8>; /* Pin 10, active low */

			};

		};



		mdio@3 {

			reg = <3>;

			#address-cells = <1>;

			#size-cells = <0>;



			phy21: ethernet-phy@1 {

				reg = <1>;

				marvell,reg-init = <3 0x10 0 0x5777>,

					<3 0x11 0 0x00aa>,

					<3 0x12 0 0x4105>,

					<3 0x13 0 0x0a60>;

				interrupt-parent = <&gpio>;

				interrupts = <12 8>; /* Pin 12, active low */

			};

			phy22: ethernet-phy@2 {

				reg = <2>;

				marvell,reg-init = <3 0x10 0 0x5777>,

					<3 0x11 0 0x00aa>,

					<3 0x12 0 0x4105>,

					<3 0x13 0 0x0a60>;

				interrupt-parent = <&gpio>;

				interrupts = <12 8>; /* Pin 12, active low */

			};

			phy23: ethernet-phy@3 {

				reg = <3>;

				marvell,reg-init = <3 0x10 0 0x5777>,

					<3 0x11 0 0x00aa>,

					<3 0x12 0 0x4105>,

					<3 0x13 0 0x0a60>;

				interrupt-parent = <&gpio>;

				interrupts = <12 8>; /* Pin 12, active low */

			};

			phy24: ethernet-phy@4 {

				reg = <4>;

				marvell,reg-init = <3 0x10 0 0x5777>,

					<3 0x11 0 0x00aa>,

					<3 0x12 0 0x4105>,

					<3 0x13 0 0x0a60>;

				interrupt-parent = <&gpio>;

				interrupts = <12 8>; /* Pin 12, active low */

			};

		};

	};

Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.



maintainers:

  - Andrew Lunn <andrew@lunn.ch>



description:

  This is a special case of a MDIO bus multiplexer.  One or more GPIO

  lines are used to control which child bus is connected.



allOf:

  - $ref: /schemas/net/mdio-mux.yaml#



properties:

  compatible:

    const: mdio-mux-gpio



  gpios:

    description:

      List of GPIOs used to control the multiplexer, least significant bit first.

    minItems: 1

    maxItems: 32



required:

  - compatible

  - gpios



unevaluatedProperties: false



examples:

  - |

    /*

     An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a

     pair of GPIO lines.  Child busses 2 and 3 populated with 4

     PHYs each.

     */

    mdio-mux {

        compatible = "mdio-mux-gpio";

        gpios = <&gpio1 3 0>, <&gpio1 4 0>;

        mdio-parent-bus = <&smi1>;

        #address-cells = <1>;

        #size-cells = <0>;



        mdio@2 {

            reg = <2>;

            #address-cells = <1>;

            #size-cells = <0>;



            ethernet-phy@1 {

                reg = <1>;

                marvell,reg-init = <3 0x10 0 0x5777>,

                  <3 0x11 0 0x00aa>,

                  <3 0x12 0 0x4105>,

                  <3 0x13 0 0x0a60>;

                interrupt-parent = <&gpio>;

                interrupts = <10 8>; /* Pin 10, active low */

            };

            ethernet-phy@2 {

                reg = <2>;

                marvell,reg-init = <3 0x10 0 0x5777>,

                  <3 0x11 0 0x00aa>,

                  <3 0x12 0 0x4105>,

                  <3 0x13 0 0x0a60>;

                interrupt-parent = <&gpio>;

                interrupts = <10 8>; /* Pin 10, active low */

            };

            ethernet-phy@3 {

                reg = <3>;

                marvell,reg-init = <3 0x10 0 0x5777>,

                  <3 0x11 0 0x00aa>,

                  <3 0x12 0 0x4105>,

                  <3 0x13 0 0x0a60>;

                interrupt-parent = <&gpio>;

                interrupts = <10 8>; /* Pin 10, active low */

            };

            ethernet-phy@4 {

                reg = <4>;

                marvell,reg-init = <3 0x10 0 0x5777>,

                  <3 0x11 0 0x00aa>,

                  <3 0x12 0 0x4105>,

                  <3 0x13 0 0x0a60>;

                interrupt-parent = <&gpio>;

                interrupts = <10 8>; /* Pin 10, active low */

            };

        };



        mdio@3 {

            reg = <3>;

            #address-cells = <1>;

            #size-cells = <0>;



            ethernet-phy@1 {

                reg = <1>;

                marvell,reg-init = <3 0x10 0 0x5777>,

                  <3 0x11 0 0x00aa>,

                  <3 0x12 0 0x4105>,

                  <3 0x13 0 0x0a60>;

                interrupt-parent = <&gpio>;

                interrupts = <12 8>; /* Pin 12, active low */

            };

            ethernet-phy@2 {

                reg = <2>;

                marvell,reg-init = <3 0x10 0 0x5777>,

                  <3 0x11 0 0x00aa>,

                  <3 0x12 0 0x4105>,

                  <3 0x13 0 0x0a60>;

                interrupt-parent = <&gpio>;

                interrupts = <12 8>; /* Pin 12, active low */

            };

            ethernet-phy@3 {

                reg = <3>;

                marvell,reg-init = <3 0x10 0 0x5777>,

                  <3 0x11 0 0x00aa>,

                  <3 0x12 0 0x4105>,

                  <3 0x13 0 0x0a60>;

                interrupt-parent = <&gpio>;

                interrupts = <12 8>; /* Pin 12, active low */

            };

            ethernet-phy@4 {

                reg = <4>;

                marvell,reg-init = <3 0x10 0 0x5777>,

                  <3 0x11 0 0x00aa>,

                  <3 0x12 0 0x4105>,

                  <3 0x13 0 0x0a60>;

                interrupt-parent = <&gpio>;

                interrupts = <12 8>; /* Pin 12, active low */

            };

        };

    };

...

Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt

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Properties for an MDIO bus multiplexer controlled by a memory-mapped device



This is a special case of a MDIO bus multiplexer.  A memory-mapped device,

like an FPGA, is used to control which child bus is connected.  The mdio-mux

node must be a child of the memory-mapped device.  The driver currently only

supports devices with 8, 16 or 32-bit registers.



Required properties in addition to the generic multiplexer properties:



- compatible : string, must contain "mdio-mux-mmioreg"



- reg : integer, contains the offset of the register that controls the bus

	multiplexer.  The size field in the 'reg' property is the size of

	register, and must therefore be 1, 2, or 4.



- mux-mask : integer, contains an eight-bit mask that specifies which

	bits in the register control the actual bus multiplexer.  The

	'reg' property of each child mdio-mux node must be constrained by

	this mask.



Example:



The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.

For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus.

A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on

BRDCFG1 that control the actual mux.



	/* The FPGA node */

	fpga: board-control@3,0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";

		reg = <3 0 0x30>;

		ranges = <0 3 0 0x30>;



		mdio-mux-emi2 {

			compatible = "mdio-mux-mmioreg", "mdio-mux";

			mdio-parent-bus = <&xmdio0>;

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <9 1>; // BRDCFG1

			mux-mask = <0x6>; // EMI2



			emi2_slot1: mdio@0 {	// Slot 1 XAUI (FM2)

				reg = <0>;

				#address-cells = <1>;

				#size-cells = <0>;



				phy_xgmii_slot1: ethernet-phy@0 {

					compatible = "ethernet-phy-ieee802.3-c45";

					reg = <4>;

				};

			};



			emi2_slot2: mdio@2 {	// Slot 2 XAUI (FM1)

				reg = <2>;

				#address-cells = <1>;

				#size-cells = <0>;



				phy_xgmii_slot2: ethernet-phy@4 {

					compatible = "ethernet-phy-ieee802.3-c45";

					reg = <0>;

				};

			};

		};

	};



	/* The parent MDIO bus. */

	xmdio0: mdio@f1000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "fsl,fman-xmdio";

		reg = <0xf1000 0x1000>;

		interrupts = <100 1 0 0>;

	};

Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device



maintainers:

  - Andrew Lunn <andrew@lunn.ch>



description: |+

  This is a special case of a MDIO bus multiplexer.  A memory-mapped device,

  like an FPGA, is used to control which child bus is connected.  The mdio-mux

  node must be a child of the memory-mapped device.  The driver currently only

  supports devices with 8, 16 or 32-bit registers.



allOf:

  - $ref: /schemas/net/mdio-mux.yaml#



properties:

  compatible:

    items:

      - const: mdio-mux-mmioreg

      - const: mdio-mux



  reg:

    description: Contains the offset of the register that controls the bus

      multiplexer. The size field in the 'reg' property is the size of register,

      and must therefore be 1, 2, or 4.

    maxItems: 1



  mux-mask:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: Contains an eight-bit mask that specifies which bits in the

      register control the actual bus multiplexer.  The 'reg' property of each

      child mdio-mux node must be constrained by this mask.



required:

  - compatible

  - reg

  - mux-mask



unevaluatedProperties: false



examples:

  - |

    mdio-mux@9 {

        compatible = "mdio-mux-mmioreg", "mdio-mux";

        mdio-parent-bus = <&xmdio0>;

        #address-cells = <1>;

        #size-cells = <0>;

        reg = <9 1>; // BRDCFG1

        mux-mask = <0x6>; // EMI2



        mdio@0 {  // Slot 1 XAUI (FM2)

            reg = <0>;

            #address-cells = <1>;

            #size-cells = <0>;



            phy_xgmii_slot1: ethernet-phy@4 {

                compatible = "ethernet-phy-ieee802.3-c45";

                reg = <4>;

            };

        };



        mdio@2 {  // Slot 2 XAUI (FM1)

            reg = <2>;

            #address-cells = <1>;

            #size-cells = <0>;



            ethernet-phy@4 {

                compatible = "ethernet-phy-ieee802.3-c45";

                reg = <4>;

            };

        };

    };

...