Commit 64a30aaf authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Add function to set pixels per cycle 



Add function to set pixels per cycle in DIG stream encoder

Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 90f33674

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

+1 −0
Original line number Diff line number Diff line
@@ -577,6 +577,7 @@ struct dcn10_stream_enc_registers { 


#define SE_REG_FIELD_LIST_DCN3_2(type) \

	type DIG_FIFO_OUTPUT_PIXEL_MODE;\

	type DP_PIXEL_PER_CYCLE_PROCESSING_MODE;\

	type DIG_SYMCLK_FE_ON;\

	type DIG_FIFO_READ_START_LEVEL;\

	type DIG_FIFO_ENABLE;\

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+2 −3
Original line number Diff line number Diff line
@@ -2535,9 +2535,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 


	tg->funcs->set_early_control(tg, early_control);



	if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)

		pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,

			timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 ? 2 : 1);

	if (dc->hwseq->funcs.set_pixels_per_cycle)

		dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx);



	/* enable audio only within mode set */

	if (pipe_ctx->stream_res.audio != NULL) {

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c

+2 −2
Original line number Diff line number Diff line
@@ -54,9 +54,9 @@ static void enc32_dp_set_odm_combine( 
	struct stream_encoder *enc,

	bool odm_combine)

{

	//struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);

	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);



	//TODO: REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);

	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine ? 1 : 0);

}



/* setup stream encoder in dvi mode */

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h

+1 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ 
#define SE_COMMON_MASK_SH_LIST_DCN32_BASE(mask_sh)\

	SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\

	SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\

	SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, mask_sh),\

	SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\

	SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\

	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+17 −0
Original line number Diff line number Diff line
@@ -1114,3 +1114,20 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign 


	return odm_combine_factor;

}



void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)

{

	uint32_t pix_per_cycle = 1;

	uint32_t odm_combine_factor = 1;



	if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)

		return;



	odm_combine_factor = get_odm_config(pipe_ctx, NULL);

	if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1)

		pix_per_cycle = 2;



	if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)

		pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,

				pix_per_cycle);

}