Commit 6490bd76 authored by Yong Zhao's avatar Yong Zhao Committed by Alex Deucher
Browse files

drm/amdgpu: Eliminate the set_pde_pte function pointer in amdgpu_gmc_funcs 



All the gmc_*_set_pde_pte functions are the same across different ASICs,
so we can eliminate the set_pde_pte function pointer and instead use a
generic function.

Signed-off-by: default avatarYong Zhao <Yong.Zhao@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3c889912

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+27 −0
Original line number Diff line number Diff line
@@ -79,6 +79,33 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 
	return pd_addr;

}



/**

 * amdgpu_gmc_set_pte_pde - update the page tables using CPU

 *

 * @adev: amdgpu_device pointer

 * @cpu_pt_addr: cpu address of the page table

 * @gpu_page_idx: entry in the page table to update

 * @addr: dst addr to write into pte/pde

 * @flags: access flags

 *

 * Update the page tables using CPU.

 */

int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,

				uint32_t gpu_page_idx, uint64_t addr,

				uint64_t flags)

{

	void __iomem *ptr = (void *)cpu_pt_addr;

	uint64_t value;



	/*

	 * The following is for PTE only. GART does not have PDEs.

	*/

	value = addr & 0x0000FFFFFFFFF000ULL;

	value |= flags;

	writeq(value, ptr + (gpu_page_idx * 8));

	return 0;

}



/**

 * amdgpu_gmc_agp_addr - return the address in the AGP address space

 *

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+3 −7
Original line number Diff line number Diff line
@@ -71,12 +71,6 @@ struct amdgpu_gmc_funcs { 
	/* Change the VMID -> PASID mapping */

	void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,

				   unsigned pasid);

	/* write pte/pde updates using the cpu */

	int (*set_pte_pde)(struct amdgpu_device *adev,

			   void *cpu_pt_addr, /* cpu addr of page table */

			   uint32_t gpu_page_idx, /* pte/pde to update */

			   uint64_t addr, /* addr to write into pte/pde */

			   uint64_t flags); /* access flags */

	/* enable/disable PRT support */

	void (*set_prt)(struct amdgpu_device *adev, bool enable);

	/* set pte flags based per asic */
@@ -155,7 +149,6 @@ struct amdgpu_gmc { 
#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type))

#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))

#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))

#define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))

#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))

#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
@@ -189,6 +182,9 @@ static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 


void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,

			       uint64_t *addr, uint64_t *flags);

int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,

				uint32_t gpu_page_idx, uint64_t addr,

				uint64_t flags);

uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);

uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);

void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

+0 −15
Original line number Diff line number Diff line
@@ -383,20 +383,6 @@ static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 
	return pd_addr;

}



static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,

				uint32_t gpu_page_idx, uint64_t addr,

				uint64_t flags)

{

	void __iomem *ptr = (void *)cpu_pt_addr;

	uint64_t value;



	value = addr & 0xFFFFFFFFFFFFF000ULL;

	value |= flags;

	writeq(value, ptr + (gpu_page_idx * 8));



	return 0;

}



static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,

					  uint32_t flags)

{
@@ -1169,7 +1155,6 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 
static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {

	.flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,

	.emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,

	.set_pte_pde = gmc_v6_0_set_pte_pde,

	.set_prt = gmc_v6_0_set_prt,

	.get_vm_pde = gmc_v6_0_get_vm_pde,

	.get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+0 −26
Original line number Diff line number Diff line
@@ -460,31 +460,6 @@ static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 
	amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);

}



/**

 * gmc_v7_0_set_pte_pde - update the page tables using MMIO

 *

 * @adev: amdgpu_device pointer

 * @cpu_pt_addr: cpu address of the page table

 * @gpu_page_idx: entry in the page table to update

 * @addr: dst addr to write into pte/pde

 * @flags: access flags

 *

 * Update the page tables using the CPU.

 */

static int gmc_v7_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,

				 uint32_t gpu_page_idx, uint64_t addr,

				 uint64_t flags)

{

	void __iomem *ptr = (void *)cpu_pt_addr;

	uint64_t value;



	value = addr & 0xFFFFFFFFFFFFF000ULL;

	value |= flags;

	writeq(value, ptr + (gpu_page_idx * 8));



	return 0;

}



static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,

					  uint32_t flags)

{
@@ -1376,7 +1351,6 @@ static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 
	.flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,

	.emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,

	.emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,

	.set_pte_pde = gmc_v7_0_set_pte_pde,

	.set_prt = gmc_v7_0_set_prt,

	.get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,

	.get_vm_pde = gmc_v7_0_get_vm_pde

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+18 −43
Original line number Diff line number Diff line
@@ -662,24 +662,6 @@ static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 
	amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);

}



/**

 * gmc_v8_0_set_pte_pde - update the page tables using MMIO

 *

 * @adev: amdgpu_device pointer

 * @cpu_pt_addr: cpu address of the page table

 * @gpu_page_idx: entry in the page table to update

 * @addr: dst addr to write into pte/pde

 * @flags: access flags

 *

 * Update the page tables using the CPU.

 */

static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,

				uint32_t gpu_page_idx, uint64_t addr,

				uint64_t flags)

{

	void __iomem *ptr = (void *)cpu_pt_addr;

	uint64_t value;



/*

 * PTE format on VI:

 * 63:40 reserved
@@ -700,12 +682,6 @@ static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 
 * bits 5:1 must be 0.

 * 0 valid

 */

	value = addr & 0x000000FFFFFFF000ULL;

	value |= flags;

	writeq(value, ptr + (gpu_page_idx * 8));



	return 0;

}



static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,

					  uint32_t flags)
@@ -1743,7 +1719,6 @@ static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 
	.flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,

	.emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,

	.emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,

	.set_pte_pde = gmc_v8_0_set_pte_pde,

	.set_prt = gmc_v8_0_set_prt,

	.get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,

	.get_vm_pde = gmc_v8_0_get_vm_pde