Commit 5df50128 authored by Lars Povlsen's avatar Lars Povlsen
Browse files

arm64: dts: sparx5: Add spi-nand devices 



This patch add spi-nand DT nodes to the applicable Sparx5 boards.

Signed-off-by: default avatarLars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
parent ba4d1c07

arch/arm64/boot/dts/microchip/sparx5.dtsi

+20 −0
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@@ -206,6 +206,26 @@ gpio: pinctrl@6110101e0 { 
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <2>;



			cs1_pins: cs1-pins {

				pins = "GPIO_16";

				function = "si";

			};



			cs2_pins: cs2-pins {

				pins = "GPIO_17";

				function = "si";

			};



			cs3_pins: cs3-pins {

				pins = "GPIO_18";

				function = "si";

			};



			si2_pins: si2-pins {

				pins = "GPIO_39", "GPIO_40", "GPIO_41";

				function = "si2";

			};



			uart_pins: uart-pins {

				pins = "GPIO_10", "GPIO_11";

				function = "uart";

arch/arm64/boot/dts/microchip/sparx5_nand.dtsi

0 → 100644
+31 −0
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.

 */



&gpio {

	cs14_pins: cs14-pins {

		pins = "GPIO_44";

		function = "si";

	};

};



&spi0 {

	pinctrl-0 = <&si2_pins>;

	pinctrl-names = "default";

	spi@e {

		compatible = "spi-mux";

		mux-controls = <&mux>;

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <14>; /* CS14 */

		spi-flash@6 {

			compatible = "spi-nand";

			pinctrl-0 = <&cs14_pins>;

			pinctrl-names = "default";

			reg = <0x6>; /* SPI2 */

			spi-max-frequency = <42000000>;

			rx-sample-delay-ns = <7>;  /* Tune for speed */

		};

	};

};

arch/arm64/boot/dts/microchip/sparx5_pcb125.dts

+14 −0
Original line number Diff line number Diff line
@@ -53,6 +53,20 @@ spi-flash@9 { 
			reg = <0x9>;	/* SPI */

		};

	};

	spi@1 {

		compatible = "spi-mux";

		mux-controls = <&mux 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <1>; /* CS1 */

		spi-flash@9 {

			compatible = "spi-nand";

			pinctrl-0 = <&cs1_pins>;

			pinctrl-names = "default";

			spi-max-frequency = <8000000>;

			reg = <0x9>;	/* SPI */

		};

	};

};



&i2c1 {

arch/arm64/boot/dts/microchip/sparx5_pcb134.dts

+1 −0
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@@ -5,6 +5,7 @@ 


/dts-v1/;

#include "sparx5_pcb134_board.dtsi"

#include "sparx5_nand.dtsi"



/ {

	model = "Sparx5 PCB134 Reference Board (NAND)";

arch/arm64/boot/dts/microchip/sparx5_pcb135.dts

+1 −0
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@@ -5,6 +5,7 @@ 


/dts-v1/;

#include "sparx5_pcb135_board.dtsi"

#include "sparx5_nand.dtsi"



/ {

	model = "Sparx5 PCB135 Reference Board (NAND)";