Commit 5cc046eb authored by Eric Biggers's avatar Eric Biggers Committed by Ulf Hansson
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dt-bindings: mmc: sdhci-msm: add ICE registers and clock 



Document the bindings for the registers and clock for the MMC instance
of the Inline Crypto Engine (ICE) on Snapdragon SoCs.  These bindings
are needed in order for sdhci-msm to support inline encryption.

Reviewed-by: default avatarSatya Tangirala <satyat@google.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarEric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20210126001456.382989-8-ebiggers@kernel.org


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 433611ea

Documentation/devicetree/bindings/mmc/sdhci-msm.txt

+3 −0
Original line number Diff line number Diff line
@@ -31,10 +31,12 @@ Required properties: 
	- SD Core register map (required for controllers earlier than msm-v5)

	- CQE register map (Optional, CQE support is present on SDHC instance meant

	                    for eMMC and version v4.2 and above)

	- Inline Crypto Engine register map (optional)

- reg-names: When CQE register map is supplied, below reg-names are required

	- "hc" for Host controller register map

	- "core" for SD core register map

	- "cqhci" for CQE register map

	- "ice" for Inline Crypto Engine register map (optional)

- interrupts: Should contain an interrupt-specifiers for the interrupts:

	- Host controller interrupt (required)

- pinctrl-names: Should contain only one value - "default".
@@ -47,6 +49,7 @@ Required properties: 
	"xo"	- TCXO clock (optional)

	"cal"	- reference clock for RCLK delay calibration (optional)

	"sleep"	- sleep clock for RCLK delay calibration (optional)

	"ice" - clock for Inline Crypto Engine (optional)



- qcom,ddr-config: Certain chipsets and platforms require particular settings

	for the DDR_CONFIG register. Use this field to specify the register