Commit 5c65ad12 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection 



This patch replaces EMMC/SDHI macros with SW_SD0_DEV_SEL DIP-Switch
macro for eMMC/SDHI device selection.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220204143132.3608-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 46da6327

arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi

+2 −12
Original line number Diff line number Diff line
@@ -8,16 +8,6 @@ 
#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>



/* SW1[2] should be at OFF position to enable 64 GB eMMC */

#define EMMC	1



/*

 * To enable uSD card on CN3,

 * SW1[2] should be at ON position.

 * Disable eMMC by setting "#define EMMC	0" above.

 */

#define SDHI	(!EMMC)



/ {

	aliases {

		ethernet0 = &eth0;
@@ -185,7 +175,7 @@ sd0_mux_uhs { 
	};

};



#if SDHI

#if (!SW_SD0_DEV_SEL)

&sdhi0 {

	pinctrl-0 = <&sdhi0_pins>;

	pinctrl-1 = <&sdhi0_pins_uhs>;
@@ -200,7 +190,7 @@ &sdhi0 { 
};

#endif



#if EMMC

#if SW_SD0_DEV_SEL

&sdhi0 {

	pinctrl-0 = <&sdhi0_emmc_pins>;

	pinctrl-1 = <&sdhi0_emmc_pins>;

arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ 
 * Please change below macros according to SW1 setting

 */



#define SW_SD0_DEV_SEL	1



#define SW_SCIF_CAN	0

#if (SW_SCIF_CAN)

/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */