Commit 5c38d48c authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Always enable the cursor right after the primary plane 



Follow the same sequence when enabling the cursor plane during
modeset. No point in doing this stuff in different order on different
generations.

This should also avoid a needless wait for vblank for the g4x cursor
workaround when the cursor gets enabled anyway.

Acked-by: default avatarEgbert Eich <eich@suse.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 63cbb074

drivers/gpu/drm/i915/intel_display.c

+4 −6
Original line number Diff line number Diff line
@@ -3219,6 +3219,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
	intel_enable_pipe(dev_priv, pipe,

			  intel_crtc->config.has_pch_encoder);

	intel_enable_plane(dev_priv, plane, pipe);

	intel_crtc_update_cursor(crtc, true);



	if (intel_crtc->config.has_pch_encoder)

		ironlake_pch_enable(crtc);
@@ -3227,8 +3228,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
	intel_update_fbc(dev);

	mutex_unlock(&dev->struct_mutex);



	intel_crtc_update_cursor(crtc, true);



	for_each_encoder_on_crtc(dev, crtc, encoder)

		encoder->enable(encoder);
@@ -3328,6 +3327,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) 
	intel_enable_pipe(dev_priv, pipe,

			  intel_crtc->config.has_pch_encoder);

	intel_enable_plane(dev_priv, plane, pipe);

	intel_crtc_update_cursor(crtc, true);



	hsw_enable_ips(intel_crtc);
@@ -3338,8 +3338,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) 
	intel_update_fbc(dev);

	mutex_unlock(&dev->struct_mutex);



	intel_crtc_update_cursor(crtc, true);



	for_each_encoder_on_crtc(dev, crtc, encoder)

		encoder->enable(encoder);
@@ -3622,12 +3620,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 


	intel_enable_pipe(dev_priv, pipe, false);

	intel_enable_plane(dev_priv, plane, pipe);

	intel_crtc_update_cursor(crtc, true);



	intel_update_fbc(dev);



	/* Give the overlay scaler a chance to enable if it's on this pipe */

	intel_crtc_dpms_overlay(intel_crtc, true);

	intel_crtc_update_cursor(crtc, true);



	mutex_unlock(&dev_priv->dpio_lock);

}
@@ -3662,6 +3660,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) 


	intel_enable_pipe(dev_priv, pipe, false);

	intel_enable_plane(dev_priv, plane, pipe);

	intel_crtc_update_cursor(crtc, true);

	if (IS_G4X(dev))

		g4x_fixup_plane(dev_priv, pipe);
@@ -3669,7 +3668,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) 


	/* Give the overlay scaler a chance to enable if it's on this pipe */

	intel_crtc_dpms_overlay(intel_crtc, true);

	intel_crtc_update_cursor(crtc, true);



	for_each_encoder_on_crtc(dev, crtc, encoder)

		encoder->enable(encoder);