Commit 5af4438f authored by YuBiao Wang's avatar YuBiao Wang Committed by Alex Deucher
Browse files

drm/amdgpu: Read clock counter via MMIO to reduce delay (v5) 



[Why]
GPU timing counters are read via KIQ under sriov, which will introduce
a delay.

[How]
It could be directly read by MMIO.

v2: Add additional check to prevent carryover issue.
v3: Only check for carryover for once to prevent performance issue.
v4: Add comments of the rough frequency where carryover happens.
v5: Remove mutex and gfxoff ctrl unused with current timing registers.

Signed-off-by: default avatarYuBiao Wang <YuBiao.Wang@amd.com>
Acked-by: default avatarHorace Chen <horace.chen@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.co>
Reviewed-by: default avatarMonk Liu <monk.liu@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 51627f03

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+14 −7
Original line number Diff line number Diff line
@@ -7605,10 +7605,8 @@ static int gfx_v10_0_soft_reset(void *handle) 


static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)

{

	uint64_t clock;

	uint64_t clock, clock_lo, clock_hi, hi_check;



	amdgpu_gfx_off_ctrl(adev, false);

	mutex_lock(&adev->gfx.gpu_clock_mutex);

	switch (adev->asic_type) {

	case CHIP_VANGOGH:

	case CHIP_YELLOW_CARP:
@@ -7616,12 +7614,21 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);

		break;

	default:

		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |

			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);

		preempt_disable();

		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);

		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);

		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);

		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over

		 * roughly every 42 seconds.

		 */

		if (hi_check != clock_hi) {

			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);

			clock_hi = hi_check;

		}

		preempt_enable();

		clock = clock_lo | (clock_hi << 32ULL);

		break;

	}

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	amdgpu_gfx_off_ctrl(adev, true);

	return clock;

}