Commit 57d4ef85 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Rob Herring
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dt-bindings: clock: renesas,r9a06g032-sysctrl: Convert to json-schema 



Convert the Renesas RZ/N1D (R9A06G032) System Controller (SYSCTRL)
Device Tree binding documentation to json-schema.

Drop the consumer example, as it doesn't belong here.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/24d1bd7c4c46747f4e2828974c2e2e48e778bff8.1620119439.git.geert+renesas@glider.be


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent aef65474

Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt

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* Renesas R9A06G032 SYSCTRL



Required Properties:



  - compatible: Must be:

    - "renesas,r9a06g032-sysctrl"

  - reg: Base address and length of the SYSCTRL IO block.

  - #clock-cells: Must be 1

  - clocks: References to the parent clocks:

	- external 40mhz crystal.

	- external (optional) 32.768khz

	- external (optional) jtag input

	- external (optional) RGMII_REFCLK

  - clock-names: Must be:

        clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";

  - #power-domain-cells: Must be 0



Examples

--------



  - SYSCTRL node:



	sysctrl: system-controller@4000c000 {

		compatible = "renesas,r9a06g032-sysctrl";

		reg = <0x4000c000 0x1000>;

		#clock-cells = <1>;



		clocks = <&ext_mclk>, <&ext_rtc_clk>,

				<&ext_jtag_clk>, <&ext_rgmii_ref>;

		clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";

		#power-domain-cells = <0>;

	};



  - Other nodes can use the clocks provided by SYSCTRL as in:



	#include <dt-bindings/clock/r9a06g032-sysctrl.h>

	uart0: serial@40060000 {

		compatible = "snps,dw-apb-uart";

		reg = <0x40060000 0x400>;

		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

		clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;

		clock-names = "baudclk", "apb_pclk";

		power-domains = <&sysctrl>;

	};

Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/N1D (R9A06G032) System Controller



maintainers:

  - Gareth Williams <gareth.williams.jx@renesas.com>

  - Geert Uytterhoeven <geert+renesas@glider.be>



properties:

  compatible:

    const: renesas,r9a06g032-sysctrl



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    items:

      - description: External 40 MHz crystal

      - description: Optional external 32.768 kHz crystal

      - description: Optional external JTAG input

      - description: Optional external RGMII_REFCLK



  clock-names:

    minItems: 1

    items:

      - const: mclk

      - const: rtc

      - const: jtag

      - const: rgmii_ref_ext



  '#clock-cells':

    const: 1



  '#power-domain-cells':

    const: 0



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    sysctrl: system-controller@4000c000 {

            compatible = "renesas,r9a06g032-sysctrl";

            reg = <0x4000c000 0x1000>;

            clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>,

                     <&ext_rgmii_ref>;

            clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";

            #clock-cells = <1>;

            #power-domain-cells = <0>;

    };