Commit 56fb7951 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
Browse files

iommu/amd: Update set_dev_entry_bit() and get_dev_entry_bit()



To include a pointer to per PCI segment device table.

Also include struct amd_iommu as one of the function parameter to
amd_iommu_apply_erratum_63() since it is needed when setting up DTE.

Co-developed-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Signed-off-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Link: https://lore.kernel.org/r/20220706113825.25582-27-vasant.hegde@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 1ab5a153
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@

extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
extern void amd_iommu_apply_erratum_63(u16 devid);
extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
extern int amd_iommu_init_devices(void);
extern void amd_iommu_uninit_devices(void);
+39 −20
Original line number Diff line number Diff line
@@ -989,22 +989,37 @@ static void iommu_enable_gt(struct amd_iommu *iommu)
}

/* sets a specific bit in the device table entry. */
static void set_dev_entry_bit(u16 devid, u8 bit)
static void __set_dev_entry_bit(struct dev_table_entry *dev_table,
				u16 devid, u8 bit)
{
	int i = (bit >> 6) & 0x03;
	int _bit = bit & 0x3f;

	amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
	dev_table[devid].data[i] |= (1UL << _bit);
}

static int get_dev_entry_bit(u16 devid, u8 bit)
static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit)
{
	struct dev_table_entry *dev_table = get_dev_table(iommu);

	return __set_dev_entry_bit(dev_table, devid, bit);
}

static int __get_dev_entry_bit(struct dev_table_entry *dev_table,
			       u16 devid, u8 bit)
{
	int i = (bit >> 6) & 0x03;
	int _bit = bit & 0x3f;

	return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
	return (dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
}

static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit)
{
	struct dev_table_entry *dev_table = get_dev_table(iommu);

	return __get_dev_entry_bit(dev_table, devid, bit);
}

static bool __copy_device_table(struct amd_iommu *iommu)
{
@@ -1123,15 +1138,15 @@ static bool copy_device_table(void)
	return true;
}

void amd_iommu_apply_erratum_63(u16 devid)
void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid)
{
	int sysmgt;

	sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
		 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
	sysmgt = get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1) |
		 (get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2) << 1);

	if (sysmgt == 0x01)
		set_dev_entry_bit(devid, DEV_ENTRY_IW);
		set_dev_entry_bit(iommu, devid, DEV_ENTRY_IW);
}

/* Writes the specific IOMMU for a device into the rlookup table */
@@ -1148,21 +1163,21 @@ static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
					   u16 devid, u32 flags, u32 ext_flags)
{
	if (flags & ACPI_DEVFLAG_INITPASS)
		set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
		set_dev_entry_bit(iommu, devid, DEV_ENTRY_INIT_PASS);
	if (flags & ACPI_DEVFLAG_EXTINT)
		set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
		set_dev_entry_bit(iommu, devid, DEV_ENTRY_EINT_PASS);
	if (flags & ACPI_DEVFLAG_NMI)
		set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
		set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS);
	if (flags & ACPI_DEVFLAG_SYSMGT1)
		set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
		set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1);
	if (flags & ACPI_DEVFLAG_SYSMGT2)
		set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
		set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2);
	if (flags & ACPI_DEVFLAG_LINT0)
		set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
		set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT0_PASS);
	if (flags & ACPI_DEVFLAG_LINT1)
		set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
		set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT1_PASS);

	amd_iommu_apply_erratum_63(devid);
	amd_iommu_apply_erratum_63(iommu, devid);

	set_iommu_for_device(iommu, devid);
}
@@ -2522,8 +2537,8 @@ static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg)
		return;

	for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
		set_dev_entry_bit(devid, DEV_ENTRY_VALID);
		set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
		__set_dev_entry_bit(dev_table, devid, DEV_ENTRY_VALID);
		__set_dev_entry_bit(dev_table, devid, DEV_ENTRY_TRANSLATION);
	}
}

@@ -2543,13 +2558,17 @@ static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg)

static void init_device_table(void)
{
	struct amd_iommu_pci_seg *pci_seg;
	u32 devid;

	if (!amd_iommu_irq_remap)
		return;

	for_each_pci_segment(pci_seg) {
		for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
		set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
			__set_dev_entry_bit(pci_seg->dev_table,
					    devid, DEV_ENTRY_IRQ_TBL_EN);
	}
}

static void iommu_init_flags(struct amd_iommu *iommu)
+1 −1
Original line number Diff line number Diff line
@@ -1607,7 +1607,7 @@ static void clear_dte_entry(struct amd_iommu *iommu, u16 devid)
	dev_table[devid].data[0]  = DTE_FLAG_V | DTE_FLAG_TV;
	dev_table[devid].data[1] &= DTE_FLAG_MASK;

	amd_iommu_apply_erratum_63(devid);
	amd_iommu_apply_erratum_63(iommu, devid);
}

static void do_attach(struct iommu_dev_data *dev_data,