Commit 56512ffd authored by Florian Fainelli's avatar Florian Fainelli
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dt-bindings: net: dsa: Document B53 SRAB interrupts and registers 



Document the Broadcom roboswitch Switch Register Access Block interrupt
lines and additional register base addresses for port mux configuration
and SGMII status/configuration registers.

Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent 046ead61

Documentation/devicetree/bindings/net/dsa/b53.txt

+36 −0
Original line number Diff line number Diff line
@@ -46,6 +46,42 @@ Required properties: 
      "brcm,bcm6328-switch"

      "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"



Required properties for BCM585xx/586xx/88312 SoCs:



 - reg: a total of 3 register base addresses, the first one must be the

   Switch Register Access block base, the second is the port 5/4 mux

   configuration register and the third one is the SGMII configuration

   and status register base address.



 - interrupts: a total of 13 interrupts must be specified, in the following

   order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,

   then the timestamping interrupt and the sleep timer interrupts for ports

   5,7,8.



Optional properties for BCM585xx/586xx/88312 SoCs:



  - reg-names: a total of 3 names matching the 3 base register address, must

    be in the following order:

	"srab"

	"mux_config"

	"sgmii_config"



  - interrupt-names: a total of 13 names matching the 13 interrupts specified

    must be in the following order:

	"link_state_p0"

	"link_state_p1"

	"link_state_p2"

	"link_state_p3"

	"link_state_p4"

	"link_state_p5"

	"link_state_p7"

	"link_state_p8"

	"phy"

	"ts"

	"imp_sleep_timer_p5"

	"imp_sleep_timer_p7"

	"imp_sleep_timer_p8"



See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional

required and optional properties.