Commit 53df89dd authored Mar 26, 2021 by Tom St Denis Committed by Alex Deucher Apr 09, 2021

drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers



Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent f41f8e08

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -6955,6 +6955,12 @@
		#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1
		#define mmCP_CE_IB2_BUFSZ 0x20cb
		#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1
		#define mmCP_IB1_BASE_LO 0x20cc
		#define mmCP_IB1_BASE_LO_BASE_IDX 1
		#define mmCP_IB1_BASE_HI 0x20cd
		#define mmCP_IB1_BASE_HI_BASE_IDX 1
		#define mmCP_IB1_BUFSZ 0x20ce
		#define mmCP_IB1_BUFSZ_BASE_IDX 1
		#define mmCP_IB2_BASE_LO 0x20cf
		#define mmCP_IB2_BASE_LO_BASE_IDX 1
		#define mmCP_IB2_BASE_HI 0x20d0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

+9 −0

Original line number	Diff line number	Diff line
		@@ -25818,6 +25818,15 @@
		//CP_CE_IB2_BUFSZ
		#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
		#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
		//CP_IB1_BASE_LO
		#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
		#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
		//CP_IB1_BASE_HI
		#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
		#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
		//CP_IB1_BUFSZ
		#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
		#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
		//CP_IB2_BASE_LO
		#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
		#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL