Loading drivers/gpu/drm/nouveau/include/nvif/class.h +4 −18 Original line number Diff line number Diff line Loading @@ -5,10 +5,10 @@ #define NVIF_CLASS_CONTROL -1 #define NVIF_CLASS_PERFMON -2 #define NVIF_CLASS_PERFDOM -3 #define NVIF_CLASS_SW_NV04 -4 #define NVIF_CLASS_SW_NV10 -5 #define NVIF_CLASS_SW_NV50 -6 #define NVIF_CLASS_SW_GF100 -7 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -4 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -5 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -6 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -7 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ #define NV_DEVICE 0x00000080 Loading Loading @@ -614,18 +614,4 @@ struct nv50_disp_overlay_v0 { }; #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 /******************************************************************************* * software ******************************************************************************/ #define NVSW_NTFY_UEVENT 0x00 #define NV04_NVSW_GET_REF 0x00 struct nv04_nvsw_get_ref_v0 { __u8 version; __u8 pad01[3]; __u32 ref; }; #endif drivers/gpu/drm/nouveau/include/nvif/if0004.h 0 → 100644 +13 −0 Original line number Diff line number Diff line #ifndef __NVIF_IF0004_H__ #define __NVIF_IF0004_H__ #define NV04_NVSW_NTFY_UEVENT 0x00 #define NV04_NVSW_GET_REF 0x00 struct nv04_nvsw_get_ref_v0 { __u8 version; __u8 pad01[3]; __u32 ref; }; #endif drivers/gpu/drm/nouveau/include/nvif/if0005.h 0 → 100644 +4 −0 Original line number Diff line number Diff line #ifndef __NVIF_IF0005_H__ #define __NVIF_IF0005_H__ #define NV10_NVSW_NTFY_UEVENT 0x00 #endif drivers/gpu/drm/nouveau/nouveau_drm.c +4 −2 Original line number Diff line number Diff line Loading @@ -37,6 +37,8 @@ #include <core/pci.h> #include <core/tegra.h> #include <nvif/if0004.h> #include "nouveau_drm.h" #include "nouveau_dma.h" #include "nouveau_ttm.h" Loading Loading @@ -256,8 +258,8 @@ nouveau_accel_init(struct nouveau_drm *drm) } ret = nvif_notify_init(&drm->nvsw, nouveau_flip_complete, false, NVSW_NTFY_UEVENT, NULL, 0, 0, &drm->flip); false, NV04_NVSW_NTFY_UEVENT, NULL, 0, 0, &drm->flip); if (ret == 0) ret = nvif_notify_get(&drm->flip); if (ret) { Loading drivers/gpu/drm/nouveau/nv04_fence.c +2 −0 Original line number Diff line number Diff line Loading @@ -26,6 +26,8 @@ #include "nouveau_dma.h" #include "nouveau_fence.h" #include <nvif/if0004.h> struct nv04_fence_chan { struct nouveau_fence_chan base; }; Loading Loading
drivers/gpu/drm/nouveau/include/nvif/class.h +4 −18 Original line number Diff line number Diff line Loading @@ -5,10 +5,10 @@ #define NVIF_CLASS_CONTROL -1 #define NVIF_CLASS_PERFMON -2 #define NVIF_CLASS_PERFDOM -3 #define NVIF_CLASS_SW_NV04 -4 #define NVIF_CLASS_SW_NV10 -5 #define NVIF_CLASS_SW_NV50 -6 #define NVIF_CLASS_SW_GF100 -7 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -4 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -5 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -6 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -7 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ #define NV_DEVICE 0x00000080 Loading Loading @@ -614,18 +614,4 @@ struct nv50_disp_overlay_v0 { }; #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 /******************************************************************************* * software ******************************************************************************/ #define NVSW_NTFY_UEVENT 0x00 #define NV04_NVSW_GET_REF 0x00 struct nv04_nvsw_get_ref_v0 { __u8 version; __u8 pad01[3]; __u32 ref; }; #endif
drivers/gpu/drm/nouveau/include/nvif/if0004.h 0 → 100644 +13 −0 Original line number Diff line number Diff line #ifndef __NVIF_IF0004_H__ #define __NVIF_IF0004_H__ #define NV04_NVSW_NTFY_UEVENT 0x00 #define NV04_NVSW_GET_REF 0x00 struct nv04_nvsw_get_ref_v0 { __u8 version; __u8 pad01[3]; __u32 ref; }; #endif
drivers/gpu/drm/nouveau/include/nvif/if0005.h 0 → 100644 +4 −0 Original line number Diff line number Diff line #ifndef __NVIF_IF0005_H__ #define __NVIF_IF0005_H__ #define NV10_NVSW_NTFY_UEVENT 0x00 #endif
drivers/gpu/drm/nouveau/nouveau_drm.c +4 −2 Original line number Diff line number Diff line Loading @@ -37,6 +37,8 @@ #include <core/pci.h> #include <core/tegra.h> #include <nvif/if0004.h> #include "nouveau_drm.h" #include "nouveau_dma.h" #include "nouveau_ttm.h" Loading Loading @@ -256,8 +258,8 @@ nouveau_accel_init(struct nouveau_drm *drm) } ret = nvif_notify_init(&drm->nvsw, nouveau_flip_complete, false, NVSW_NTFY_UEVENT, NULL, 0, 0, &drm->flip); false, NV04_NVSW_NTFY_UEVENT, NULL, 0, 0, &drm->flip); if (ret == 0) ret = nvif_notify_get(&drm->flip); if (ret) { Loading
drivers/gpu/drm/nouveau/nv04_fence.c +2 −0 Original line number Diff line number Diff line Loading @@ -26,6 +26,8 @@ #include "nouveau_dma.h" #include "nouveau_fence.h" #include <nvif/if0004.h> struct nv04_fence_chan { struct nouveau_fence_chan base; }; Loading