Commit 5372350b authored by Mike Rapoport's avatar Mike Rapoport Committed by Greg Kroah-Hartman
Browse files

staging: sm750fb: use BIT macro for MISC_CTRL single-bit fields 



Replace complex definition of MISC_CTRL register fields with BIT() macro
and use open-coded implementation for register manipulations.

Signed-off-by: default avatarMike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8bc728cf

drivers/staging/sm750fb/ddk750_chip.c

+2 −2
Original line number Diff line number Diff line
@@ -239,10 +239,10 @@ int ddk750_initHw(initchip_param_t *pInitParam) 
	 */

	if (pInitParam->resetMemory == 1) {

		reg = PEEK32(MISC_CTRL);

		reg = FIELD_SET(reg, MISC_CTRL, LOCALMEM_RESET, RESET);

		reg &= ~MISC_CTRL_LOCALMEM_RESET;

		POKE32(MISC_CTRL, reg);



		reg = FIELD_SET(reg, MISC_CTRL, LOCALMEM_RESET, NORMAL);

		reg |= MISC_CTRL_LOCALMEM_RESET;

		POKE32(MISC_CTRL, reg);

	}

drivers/staging/sm750fb/ddk750_power.h

+4 −7
Original line number Diff line number Diff line
@@ -9,12 +9,9 @@ typedef enum _DPMS_t { 
}

DPMS_t;



#define setDAC(off) \

		{	\

		POKE32(MISC_CTRL, FIELD_VALUE(PEEK32(MISC_CTRL), \

									MISC_CTRL,	\

									DAC_POWER,	\

									off));	\

#define setDAC(off) {							\

	POKE32(MISC_CTRL,						\

	       (PEEK32(MISC_CTRL) & ~MISC_CTRL_DAC_POWER_OFF) | (off)); \

}



void ddk750_setDPMS(DPMS_t);

drivers/staging/sm750fb/ddk750_reg.h

+17 −51
Original line number Diff line number Diff line
@@ -42,26 +42,16 @@ 
#define SYSTEM_CTRL_PANEL_TRISTATE                    BIT(0)



#define MISC_CTRL                                     0x000004

#define MISC_CTRL_DRAM_RERESH_COUNT                   27:27

#define MISC_CTRL_DRAM_RERESH_COUNT_1ROW              0

#define MISC_CTRL_DRAM_RERESH_COUNT_3ROW              1

#define MISC_CTRL_DRAM_RERESH_COUNT                   BIT(27)

#define MISC_CTRL_DRAM_REFRESH_TIME                   26:25

#define MISC_CTRL_DRAM_REFRESH_TIME_8                 0

#define MISC_CTRL_DRAM_REFRESH_TIME_16                1

#define MISC_CTRL_DRAM_REFRESH_TIME_32                2

#define MISC_CTRL_DRAM_REFRESH_TIME_64                3

#define MISC_CTRL_INT_OUTPUT                          24:24

#define MISC_CTRL_INT_OUTPUT_NORMAL                   0

#define MISC_CTRL_INT_OUTPUT_INVERT                   1

#define MISC_CTRL_PLL_CLK_COUNT                       23:23

#define MISC_CTRL_PLL_CLK_COUNT_OFF                   0

#define MISC_CTRL_PLL_CLK_COUNT_ON                    1

#define MISC_CTRL_DAC_POWER                           20:20

#define MISC_CTRL_DAC_POWER_ON                        0

#define MISC_CTRL_DAC_POWER_OFF                       1

#define MISC_CTRL_CLK_SELECT                          16:16

#define MISC_CTRL_CLK_SELECT_OSC                      0

#define MISC_CTRL_CLK_SELECT_TESTCLK                  1

#define MISC_CTRL_INT_OUTPUT_INVERT                   BIT(24)

#define MISC_CTRL_PLL_CLK_COUNT                       BIT(23)

#define MISC_CTRL_DAC_POWER_OFF                       BIT(20)

#define MISC_CTRL_CLK_SELECT_TESTCLK                  BIT(16)

#define MISC_CTRL_DRAM_COLUMN_SIZE                    15:14

#define MISC_CTRL_DRAM_COLUMN_SIZE_256                0

#define MISC_CTRL_DRAM_COLUMN_SIZE_512                1
@@ -71,42 +61,18 @@ 
#define MISC_CTRL_LOCALMEM_SIZE_16M                   0

#define MISC_CTRL_LOCALMEM_SIZE_32M                   1

#define MISC_CTRL_LOCALMEM_SIZE_64M                   2

#define MISC_CTRL_DRAM_TWTR                           11:11

#define MISC_CTRL_DRAM_TWTR_2CLK                      0

#define MISC_CTRL_DRAM_TWTR_1CLK                      1

#define MISC_CTRL_DRAM_TWR                            10:10

#define MISC_CTRL_DRAM_TWR_3CLK                       0

#define MISC_CTRL_DRAM_TWR_2CLK                       1

#define MISC_CTRL_DRAM_TRP                            9:9

#define MISC_CTRL_DRAM_TRP_3CLK                       0

#define MISC_CTRL_DRAM_TRP_4CLK                       1

#define MISC_CTRL_DRAM_TRFC                           8:8

#define MISC_CTRL_DRAM_TRFC_12CLK                     0

#define MISC_CTRL_DRAM_TRFC_14CLK                     1

#define MISC_CTRL_DRAM_TRAS                           7:7

#define MISC_CTRL_DRAM_TRAS_7CLK                      0

#define MISC_CTRL_DRAM_TRAS_8CLK                      1

#define MISC_CTRL_LOCALMEM_RESET                      6:6

#define MISC_CTRL_LOCALMEM_RESET_RESET                0

#define MISC_CTRL_LOCALMEM_RESET_NORMAL               1

#define MISC_CTRL_LOCALMEM_STATE                      5:5

#define MISC_CTRL_LOCALMEM_STATE_ACTIVE               0

#define MISC_CTRL_LOCALMEM_STATE_INACTIVE             1

#define MISC_CTRL_CPU_CAS_LATENCY                     4:4

#define MISC_CTRL_CPU_CAS_LATENCY_2CLK                0

#define MISC_CTRL_CPU_CAS_LATENCY_3CLK                1

#define MISC_CTRL_DLL                                 3:3

#define MISC_CTRL_DLL_ON                              0

#define MISC_CTRL_DLL_OFF                             1

#define MISC_CTRL_DRAM_OUTPUT                         2:2

#define MISC_CTRL_DRAM_OUTPUT_LOW                     0

#define MISC_CTRL_DRAM_OUTPUT_HIGH                    1

#define MISC_CTRL_LOCALMEM_BUS_SIZE                   1:1

#define MISC_CTRL_LOCALMEM_BUS_SIZE_32                0

#define MISC_CTRL_LOCALMEM_BUS_SIZE_64                1

#define MISC_CTRL_EMBEDDED_LOCALMEM                   0:0

#define MISC_CTRL_EMBEDDED_LOCALMEM_ON                0

#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF               1

#define MISC_CTRL_DRAM_TWTR                           BIT(11)

#define MISC_CTRL_DRAM_TWR                            BIT(10)

#define MISC_CTRL_DRAM_TRP                            BIT(9)

#define MISC_CTRL_DRAM_TRFC                           BIT(8)

#define MISC_CTRL_DRAM_TRAS                           BIT(7)

#define MISC_CTRL_LOCALMEM_RESET                      BIT(6)

#define MISC_CTRL_LOCALMEM_STATE_INACTIVE             BIT(5)

#define MISC_CTRL_CPU_CAS_LATENCY                     BIT(4)

#define MISC_CTRL_DLL_OFF                             BIT(3)

#define MISC_CTRL_DRAM_OUTPUT_HIGH                    BIT(2)

#define MISC_CTRL_LOCALMEM_BUS_SIZE                   BIT(1)

#define MISC_CTRL_EMBEDDED_LOCALMEM_OFF               BIT(0)



#define GPIO_MUX                                      0x000008

#define GPIO_MUX_31                                   31:31

drivers/staging/sm750fb/sm750_hw.c

+2 −6
Original line number Diff line number Diff line
@@ -116,18 +116,14 @@ int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev) 
		/* does user need CRT ?*/

		if (sm750_dev->nocrt) {

			POKE32(MISC_CTRL,

					FIELD_SET(PEEK32(MISC_CTRL),

					MISC_CTRL,

					DAC_POWER, OFF));

			       PEEK32(MISC_CTRL) | MISC_CTRL_DAC_POWER_OFF);

			/* shut off dpms */

			val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;

			val |= SYSTEM_CTRL_DPMS_VPHN;

			POKE32(SYSTEM_CTRL, val);

		} else {

			POKE32(MISC_CTRL,

					FIELD_SET(PEEK32(MISC_CTRL),

					MISC_CTRL,

					DAC_POWER, ON));

			       PEEK32(MISC_CTRL) & ~MISC_CTRL_DAC_POWER_OFF);

			/* turn on dpms */

			val = PEEK32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;

			val |= SYSTEM_CTRL_DPMS_VPHP;