Commit 536fbf94 authored by Ken Wang's avatar Ken Wang Committed by Alex Deucher
Browse files

drm/amdgpu: change wptr to 64 bits (v2) 



Newer asics need 64 bit wptrs.  If the wptr is now
smaller than the rptr that doesn't indicate a wrap-around
anymore.

v2: integrate Christian's comments.

Signed-off-by: default avatarKen Wang <Qingqing.Wang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8fe73328

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Diff line number Diff line
@@ -1601,7 +1601,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 
{

	if (ring->count_dw <= 0)

		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	ring->ring[ring->wptr++] = v;

	ring->ring[ring->wptr++ & ring->buf_mask] = v;

	ring->wptr &= ring->ptr_mask;

	ring->count_dw--;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

+4 −1
Original line number Diff line number Diff line
@@ -232,7 +232,10 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 
		}

		amdgpu_ring_clear_ring(ring);

	}

	ring->ptr_mask = (ring->ring_size / 4) - 1;

	ring->buf_mask = (ring->ring_size / 4) - 1;

	ring->ptr_mask = ring->funcs->support_64bit_ptrs ?

		0xffffffffffffffff : ring->buf_mask;



	ring->max_dw = max_dw;



	if (amdgpu_debugfs_ring_init(adev, ring)) {

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+7 −5
Original line number Diff line number Diff line
@@ -96,10 +96,11 @@ struct amdgpu_ring_funcs { 
	enum amdgpu_ring_type	type;

	uint32_t		align_mask;

	u32			nop;

	bool			support_64bit_ptrs;



	/* ring read/write ptr handling */

	u32 (*get_rptr)(struct amdgpu_ring *ring);

	u32 (*get_wptr)(struct amdgpu_ring *ring);

	u64 (*get_rptr)(struct amdgpu_ring *ring);

	u64 (*get_wptr)(struct amdgpu_ring *ring);

	void (*set_wptr)(struct amdgpu_ring *ring);

	/* validating and patching of IBs */

	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
@@ -148,13 +149,14 @@ struct amdgpu_ring { 
	struct amdgpu_bo	*ring_obj;

	volatile uint32_t	*ring;

	unsigned		rptr_offs;

	unsigned		wptr;

	unsigned		wptr_old;

	u64			wptr;

	u64			wptr_old;

	unsigned		ring_size;

	unsigned		max_dw;

	int			count_dw;

	uint64_t		gpu_addr;

	uint32_t		ptr_mask;

	uint64_t		ptr_mask;

	uint32_t		buf_mask;

	bool			ready;

	u32			idx;

	u32			me;

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+7 −5
Original line number Diff line number Diff line
@@ -158,7 +158,7 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev) 
 *

 * Get the current rptr from the hardware (CIK+).

 */

static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)

static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)

{

	u32 rptr;
@@ -174,7 +174,7 @@ static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) 
 *

 * Get the current wptr from the hardware (CIK+).

 */

static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)

static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
@@ -194,7 +194,8 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) 
	struct amdgpu_device *adev = ring->adev;

	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;



	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);

	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],

		       	(lower_32_bits(ring->wptr) << 2) & 0x3fffc);

}



static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@@ -225,7 +226,7 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 
	u32 extra_bits = vm_id & 0xf;



	/* IB packet must end on a 8 DW boundary */

	cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);

	cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);



	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));

	amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
@@ -432,7 +433,7 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 
		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);



		ring->wptr = 0;

		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);

		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);



		/* enable DMA RB */

		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
@@ -1209,6 +1210,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 
	.type = AMDGPU_RING_TYPE_SDMA,

	.align_mask = 0xf,

	.nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),

	.support_64bit_ptrs = false,

	.get_rptr = cik_sdma_ring_get_rptr,

	.get_wptr = cik_sdma_ring_get_wptr,

	.set_wptr = cik_sdma_ring_set_wptr,

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+6 −5
Original line number Diff line number Diff line
@@ -2192,12 +2192,12 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 
	return 0;

}



static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)

static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)

{

	return ring->adev->wb.wb[ring->rptr_offs];

}



static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)

static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;
@@ -2215,7 +2215,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 
{

	struct amdgpu_device *adev = ring->adev;



	WREG32(mmCP_RB0_WPTR, ring->wptr);

	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

	(void)RREG32(mmCP_RB0_WPTR);

}
@@ -2224,10 +2224,10 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 
	struct amdgpu_device *adev = ring->adev;



	if (ring == &adev->gfx.compute_ring[0]) {

		WREG32(mmCP_RB1_WPTR, ring->wptr);

		WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));

		(void)RREG32(mmCP_RB1_WPTR);

	} else if (ring == &adev->gfx.compute_ring[1]) {

		WREG32(mmCP_RB2_WPTR, ring->wptr);

		WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));

		(void)RREG32(mmCP_RB2_WPTR);

	} else {

		BUG();
@@ -3631,6 +3631,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 
	.type = AMDGPU_RING_TYPE_GFX,

	.align_mask = 0xff,

	.nop = 0x80000000,

	.support_64bit_ptrs = false,

	.get_rptr = gfx_v6_0_ring_get_rptr,

	.get_wptr = gfx_v6_0_ring_get_wptr,

	.set_wptr = gfx_v6_0_ring_set_wptr_gfx,