Commit 51a0f370 authored by Thierry Reding's avatar Thierry Reding
Browse files

dt-bindings: misc: Convert Tegra MISC to json-schema 



Convert the device tree bindings for the MISC register block found on
NVIDIA Tegra SoCs from plain text to json-schema format.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 57978838

Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt

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NVIDIA Tegra186 (and later) MISC register block



The MISC register block found on Tegra186 and later SoCs contains registers

that can be used to identify a given chip and various strapping options.



Required properties:

- compatible: Must be:

  - Tegra186: "nvidia,tegra186-misc"

  - Tegra194: "nvidia,tegra194-misc"

  - Tegra234: "nvidia,tegra234-misc"

- reg: Should contain 2 entries: The first entry gives the physical address

       and length of the register region which contains revision and debug

       features. The second entry specifies the physical address and length

       of the register region indicating the strapping options.

Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra186 (and later) MISC register block



maintainers:

  - Thierry Reding <thierry.reding@gmail.com>

  - Jon Hunter <jonathanh@nvidia.com>



description: The MISC register block found on Tegra186 and later SoCs contains

  registers that can be used to identify a given chip and various strapping

  options.



properties:

  compatible:

    enum:

      - nvidia,tegra186-misc

      - nvidia,tegra194-misc

      - nvidia,tegra234-misc



  reg:

    items:

      - description: physical address and length of the registers which

          contain revision and debug features

      - description: physical address and length of the registers which

          indicate strapping options



additionalProperties: false



required:

  - compatible

  - reg



examples:

  - |

    misc@100000 {

        compatible = "nvidia,tegra186-misc";

        reg = <0x00100000 0xf000>,

              <0x0010f000 0x1000>;

    };

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt

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NVIDIA Tegra APBMISC block



Required properties:

- compatible: Must be:

  - Tegra20: "nvidia,tegra20-apbmisc"

  - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"

  - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"

  - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"

  - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"

  - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"

- reg: Should contain 2 entries: the first entry gives the physical address

       and length of the registers which contain revision and debug features.

       The second entry gives the physical address and length of the

       registers indicating the strapping options.



Optional properties:

- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra APBMISC block



maintainers:

  - Thierry Reding <thierry.reding@gmail.com>

  - Jon Hunter <jonathanh@nvidia.com>



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - nvidia,tegra210-apbmisc

              - nvidia,tegra124-apbmisc

              - nvidia,tegra114-apbmisc

              - nvidia,tegra30-apbmisc

          - const: nvidia,tegra20-apbmisc



      - items:

          - const: nvidia,tegra20-apbmisc



  reg:

    items:

      - description: physical address and length of the registers which

          contain revision and debug features

      - description: physical address and length of the registers which

          indicate strapping options



  nvidia,long-ram-code:

    description: If present, the RAM code is long (4 bit). If not, short

      (2 bit).

    type: boolean



additionalProperties: false



required:

  - compatible

  - reg



examples:

  - |

    apbmisc@70000800 {

        compatible = "nvidia,tegra20-apbmisc";

        reg = <0x70000800 0x64>, /* Chip revision */

              <0x70000008 0x04>; /* Strapping options */

    };