Commit 519607a2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN



No need for a separate kconfig option at this point.

Reviewed-by: default avatarZhan Liu <zhan.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8001ba85
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@@ -17,15 +17,6 @@ config DRM_AMD_DC_DCN
	help
	  Raven, Navi, and newer family support for display engine

config DRM_AMD_DC_DCN201
	bool "Enable DCN201 support in DC"
	default y
	depends on DRM_AMD_DC && X86
	depends on DRM_AMD_DC_DCN
	help
	  Choose this option if you want to have
	  201 support for display engine

config DRM_AMD_DC_HDCP
	bool "Enable HDCP support in DC"
	depends on DRM_AMD_DC
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@@ -30,9 +30,7 @@ DC_LIBS += dcn20
DC_LIBS += dsc
DC_LIBS += dcn10 dml
DC_LIBS += dcn21
ifdef CONFIG_DRM_AMD_DC_DCN201
DC_LIBS += dcn201
endif
DC_LIBS += dcn30
DC_LIBS += dcn301
DC_LIBS += dcn302
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@@ -93,7 +93,6 @@ AMD_DAL_CLK_MGR_DCN20 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DC

AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20)

ifdef CONFIG_DRM_AMD_DC_DCN201
###############################################################################
# DCN201
###############################################################################
@@ -102,7 +101,6 @@ CLK_MGR_DCN201 = dcn201_clk_mgr.o
AMD_DAL_CLK_MGR_DCN201 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn201/,$(CLK_MGR_DCN201))

AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN201)
endif

###############################################################################
# DCN21
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@@ -257,12 +257,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
			return &clk_mgr->base;
		}
#if defined(CONFIG_DRM_AMD_DC_DCN201)
		if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
			dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
			return &clk_mgr->base;
		}
#endif
		dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
		return &clk_mgr->base;
	}
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@@ -224,11 +224,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
	case DCN_VERSION_2_1:
		res_pool = dcn21_create_resource_pool(init_data, dc);
		break;
#if defined(CONFIG_DRM_AMD_DC_DCN201)
	case DCN_VERSION_2_01:
		res_pool = dcn201_create_resource_pool(init_data, dc);
		break;
#endif
	case DCN_VERSION_3_0:
		res_pool = dcn30_create_resource_pool(init_data, dc);
		break;
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