Loading drivers/media/dvb/ddbridge/ddbridge-core.c +109 −82 Original line number Diff line number Diff line Loading @@ -89,10 +89,10 @@ static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); if (stat <= 0) { printk("I2C timeout\n"); printk(KERN_ERR "I2C timeout\n"); { /* MSI debugging*/ u32 istat = ddbreadl(INTERRUPT_STATUS); printk("IRS %08x\n", istat); printk(KERN_ERR "IRS %08x\n", istat); ddbwritel(istat, INTERRUPT_ACK); } return -EIO; Loading Loading @@ -217,6 +217,7 @@ static int ddb_i2c_init(struct ddb *dev) /******************************************************************************/ /******************************************************************************/ #if 0 static void set_table(struct ddb *dev, u32 off, dma_addr_t *pbuf, u32 num) { Loading @@ -230,6 +231,7 @@ static void set_table(struct ddb *dev, u32 off, ddbwritel(mem >> 32, base + i * 8 + 4); } } #endif static void ddb_address_table(struct ddb *dev) { Loading Loading @@ -401,7 +403,7 @@ static void ddb_output_start(struct ddb_output *output) ddbwritel(1, DMA_BASE_READ); ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); //ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */ ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); output->running = 1; spin_unlock_irq(&output->lock); Loading Loading @@ -496,7 +498,7 @@ static u32 ddb_input_avail(struct ddb_input *input) off = (stat & 0x7ff) << 7; if (ctrl & 4) { printk("IA %d %d %08x\n", idx, off, ctrl); printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl); ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); return 0; } Loading Loading @@ -577,7 +579,7 @@ static int demod_attach_drxk(struct ddb_input *input) i2c, 0x29 + (input->nr&1), &input->fe2); if (!input->fe) { printk("No DRXK found!\n"); printk(KERN_ERR "No DRXK found!\n"); return -ENODEV; } fe->sec_priv = input; Loading @@ -595,7 +597,7 @@ static int tuner_attach_tda18271(struct ddb_input *input) input->fe->ops.i2c_gate_ctrl(input->fe, 1); fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); if (!fe) { printk("No TDA18271 found!\n"); printk(KERN_ERR "No TDA18271 found!\n"); return -ENODEV; } if (input->fe->ops.i2c_gate_ctrl) Loading Loading @@ -666,13 +668,13 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) (input->nr & 1) ? STV090x_DEMODULATOR_1 : STV090x_DEMODULATOR_0); if (!input->fe) { printk("No STV0900 found!\n"); printk(KERN_ERR "No STV0900 found!\n"); return -ENODEV; } if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, 0, (input->nr & 1) ? (0x09 - type) : (0x0b - type))) { printk("No LNBH24 found!\n"); printk(KERN_ERR "No LNBH24 found!\n"); return -ENODEV; } return 0; Loading @@ -688,10 +690,11 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type) ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); if (!ctl) { printk("No STV6110X found!\n"); printk(KERN_ERR "No STV6110X found!\n"); return -ENODEV; } printk("attach tuner input %d adr %02x\n", input->nr, tunerconf->addr); printk(KERN_INFO "attach tuner input %d adr %02x\n", input->nr, tunerconf->addr); feconf->tuner_init = ctl->tuner_init; feconf->tuner_sleep = ctl->tuner_sleep; Loading Loading @@ -817,7 +820,7 @@ static int dvb_input_attach(struct ddb_input *input) &input->port->dev->pdev->dev, adapter_nr); if (ret < 0) { printk("ddbridge: Could not register adapter." printk(KERN_ERR "ddbridge: Could not register adapter." "Check if you enabled enough adapters in dvb-core!\n"); return ret; } Loading Loading @@ -942,9 +945,11 @@ static ssize_t ts_read(struct file *file, char *buf, static unsigned int ts_poll(struct file *file, poll_table *wait) { /* struct dvb_device *dvbdev = file->private_data; struct ddb_output *output = dvbdev->priv; struct ddb_input *input = output->port->input[0]; */ unsigned int mask = 0; #if 0 Loading @@ -959,7 +964,7 @@ static unsigned int ts_poll(struct file *file, poll_table *wait) return mask; } static struct file_operations ci_fops = { static const struct file_operations ci_fops = { .owner = THIS_MODULE, .read = ts_read, .write = ts_write, Loading Loading @@ -995,7 +1000,7 @@ static void input_tasklet(unsigned long data) if (input->port->class == DDB_PORT_TUNER) { if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) printk("Overflow input %d\n", input->nr); printk(KERN_ERR "Overflow input %d\n", input->nr); while (input->cbuf != ((input->stat >> 11) & 0x1f) || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { dvb_dmx_swfilter_packets(&input->demux, Loading Loading @@ -1080,7 +1085,7 @@ static int ddb_port_attach(struct ddb_port *port) break; } if (ret < 0) printk("port_attach on port %d failed\n", port->nr); printk(KERN_ERR "port_attach on port %d failed\n", port->nr); return ret; } Loading Loading @@ -1132,7 +1137,7 @@ static void ddb_ports_detach(struct ddb *dev) static int port_has_ci(struct ddb_port *port) { u8 val; return (i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1); return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; } static int port_has_stv0900(struct ddb_port *port) Loading Loading @@ -1188,7 +1193,8 @@ static void ddb_port_probe(struct ddb_port *port) port->type = DDB_TUNER_DVBCT_TR; ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); } printk("Port %d (TAB %d): %s\n", port->nr, port->nr+1, modname); printk(KERN_INFO "Port %d (TAB %d): %s\n", port->nr, port->nr+1, modname); } static void ddb_input_init(struct ddb_port *port, int nr) Loading Loading @@ -1284,26 +1290,42 @@ static irqreturn_t irq_handler(int irq, void *dev_id) do { ddbwritel(s, INTERRUPT_ACK); if (s & 0x00000001) irq_handle_i2c(dev, 0); if (s & 0x00000002) irq_handle_i2c(dev, 1); if (s & 0x00000004) irq_handle_i2c(dev, 2); if (s & 0x00000008) irq_handle_i2c(dev, 3); if (s & 0x00000100) tasklet_schedule(&dev->input[0].tasklet); if (s & 0x00000200) tasklet_schedule(&dev->input[1].tasklet); if (s & 0x00000400) tasklet_schedule(&dev->input[2].tasklet); if (s & 0x00000800) tasklet_schedule(&dev->input[3].tasklet); if (s & 0x00001000) tasklet_schedule(&dev->input[4].tasklet); if (s & 0x00002000) tasklet_schedule(&dev->input[5].tasklet); if (s & 0x00004000) tasklet_schedule(&dev->input[6].tasklet); if (s & 0x00008000) tasklet_schedule(&dev->input[7].tasklet); if (s & 0x00010000) tasklet_schedule(&dev->output[0].tasklet); if (s & 0x00020000) tasklet_schedule(&dev->output[1].tasklet); if (s & 0x00040000) tasklet_schedule(&dev->output[2].tasklet); if (s & 0x00080000) tasklet_schedule(&dev->output[3].tasklet); /* if (s & 0x000f0000) printk("%08x\n", istat); */ if (s & 0x00000001) irq_handle_i2c(dev, 0); if (s & 0x00000002) irq_handle_i2c(dev, 1); if (s & 0x00000004) irq_handle_i2c(dev, 2); if (s & 0x00000008) irq_handle_i2c(dev, 3); if (s & 0x00000100) tasklet_schedule(&dev->input[0].tasklet); if (s & 0x00000200) tasklet_schedule(&dev->input[1].tasklet); if (s & 0x00000400) tasklet_schedule(&dev->input[2].tasklet); if (s & 0x00000800) tasklet_schedule(&dev->input[3].tasklet); if (s & 0x00001000) tasklet_schedule(&dev->input[4].tasklet); if (s & 0x00002000) tasklet_schedule(&dev->input[5].tasklet); if (s & 0x00004000) tasklet_schedule(&dev->input[6].tasklet); if (s & 0x00008000) tasklet_schedule(&dev->input[7].tasklet); if (s & 0x00010000) tasklet_schedule(&dev->output[0].tasklet); if (s & 0x00020000) tasklet_schedule(&dev->output[1].tasklet); if (s & 0x00040000) tasklet_schedule(&dev->output[2].tasklet); if (s & 0x00080000) tasklet_schedule(&dev->output[3].tasklet); /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ } while ((s = ddbreadl(INTERRUPT_STATUS))); return IRQ_HANDLED; Loading @@ -1325,7 +1347,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) wbuf += 4; wlen -= 4; ddbwritel(data, SPI_DATA); while (ddbreadl(SPI_CONTROL) & 0x0004); while (ddbreadl(SPI_CONTROL) & 0x0004) ; } if (rlen) Loading @@ -1344,7 +1367,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) if (shift) data <<= shift; ddbwritel(data, SPI_DATA); while (ddbreadl(SPI_CONTROL) & 0x0004); while (ddbreadl(SPI_CONTROL) & 0x0004) ; if (!rlen) { ddbwritel(0, SPI_CONTROL); Loading @@ -1355,7 +1379,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) while (rlen > 4) { ddbwritel(0xffffffff, SPI_DATA); while (ddbreadl(SPI_CONTROL) & 0x0004); while (ddbreadl(SPI_CONTROL) & 0x0004) ; data = ddbreadl(SPI_DATA); *(u32 *) rbuf = swab32(data); rbuf += 4; Loading @@ -1363,7 +1388,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) } ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); ddbwritel(0xffffffff, SPI_DATA); while (ddbreadl(SPI_CONTROL) & 0x0004); while (ddbreadl(SPI_CONTROL) & 0x0004) ; data = ddbreadl(SPI_DATA); ddbwritel(0, SPI_CONTROL); Loading Loading @@ -1421,7 +1447,7 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) if (copy_from_user(&fio, parg, sizeof(fio))) break; if (fio.write_len + fio.read_len > 1028) { printk("IOBUF too small\n"); printk(KERN_ERR "IOBUF too small\n"); return -ENOMEM; } wbuf = &dev->iobuf[0]; Loading @@ -1444,7 +1470,7 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) return res; } static struct file_operations ddb_fops={ static const struct file_operations ddb_fops = { .unlocked_ioctl = ddb_ioctl, .open = ddb_open, }; Loading @@ -1458,7 +1484,8 @@ static char *ddb_devnode(struct device *device, mode_t *mode) static int ddb_class_create(void) { if ((ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops))<0) ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); if (ddb_major < 0) return ddb_major; ddb_class = class_create(THIS_MODULE, DDB_NAME); Loading Loading @@ -1550,7 +1577,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev, dev->pdev = pdev; pci_set_drvdata(pdev, dev); dev->info = (struct ddb_info *) id->driver_data; printk("DDBridge driver detected: %s\n", dev->info->name); printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); dev->regs = ioremap(pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); Loading @@ -1558,7 +1585,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev, stat = -ENOMEM; goto fail; } printk("HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); #ifdef CONFIG_PCI_MSI if (pci_msi_enabled()) Loading @@ -1570,9 +1597,9 @@ static int __devinit ddb_probe(struct pci_dev *pdev, dev->msi = 1; } #endif if ((stat = request_irq(dev->pdev->irq, irq_handler, irq_flag, "DDBridge", (void *) dev))<0) stat = request_irq(dev->pdev->irq, irq_handler, irq_flag, "DDBridge", (void *) dev); if (stat < 0) goto fail1; ddbwritel(0, DMA_BASE_WRITE); ddbwritel(0, DMA_BASE_READ); Loading @@ -1594,18 +1621,18 @@ static int __devinit ddb_probe(struct pci_dev *pdev, fail3: ddb_ports_detach(dev); printk("fail3\n"); printk(KERN_ERR "fail3\n"); ddb_ports_release(dev); fail2: printk("fail2\n"); printk(KERN_ERR "fail2\n"); ddb_buffers_free(dev); fail1: printk("fail1\n"); printk(KERN_ERR "fail1\n"); if (dev->msi) pci_disable_msi(dev->pdev); free_irq(dev->pdev->irq, dev); fail: printk("fail\n"); printk(KERN_ERR "fail\n"); ddb_unmap(dev); pci_set_drvdata(pdev, 0); pci_disable_device(pdev); Loading Loading @@ -1668,7 +1695,7 @@ static struct pci_driver ddb_pci_driver = { static __init int module_init_ddbridge(void) { printk("Digital Devices PCIE bridge driver, " printk(KERN_INFO "Digital Devices PCIE bridge driver, " "Copyright (C) 2010-11 Digital Devices GmbH\n"); if (ddb_class_create()) return -1; Loading drivers/media/dvb/ddbridge/ddbridge-regs.h +31 −31 Original line number Diff line number Diff line Loading @@ -21,26 +21,26 @@ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html */ // $Id: DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred $ /* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */ // Register Definitions /* Register Definitions */ #define CUR_REGISTERMAP_VERSION 0x10000 #define HARDWARE_VERSION 0x00 #define REGISTERMAP_VERSION 0x04 // -------------------------------------------------------------------------- // SPI Controller /* ------------------------------------------------------------------------- */ /* SPI Controller */ #define SPI_CONTROL 0x10 #define SPI_DATA 0x14 // -------------------------------------------------------------------------- /* ------------------------------------------------------------------------- */ // Interrupt controller // How many MSI's are available depends on HW (Min 2 max 8) // How many are usable also depends on Host platform /* Interrupt controller */ /* How many MSI's are available depends on HW (Min 2 max 8) */ /* How many are usable also depends on Host platform */ #define INTERRUPT_BASE (0x40) Loading Loading @@ -81,15 +81,15 @@ #define INTMASK_TSOUTPUT3 (0x00040000) #define INTMASK_TSOUTPUT4 (0x00080000) // -------------------------------------------------------------------------- // I2C Master Controller /* ------------------------------------------------------------------------- */ /* I2C Master Controller */ #define I2C_BASE (0x80) // Byte offset #define I2C_BASE (0x80) /* Byte offset */ #define I2C_COMMAND (0x00) #define I2C_TIMING (0x04) #define I2C_TASKLENGTH (0x08) // High read, low write #define I2C_TASKADDRESS (0x0C) // High read, low write #define I2C_TASKLENGTH (0x08) /* High read, low write */ #define I2C_TASKADDRESS (0x0C) /* High read, low write */ #define I2C_MONITOR (0x1C) Loading @@ -100,7 +100,7 @@ #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) #define I2C_TASKMEM_BASE (0x1000) // Byte offset #define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ #define I2C_TASKMEM_SIZE (0x1000) #define I2C_SPEED_400 (0x04030404) Loading @@ -111,27 +111,27 @@ #define I2C_SPEED_50 (0x27262727) // -------------------------------------------------------------------------- // DMA Controller /* ------------------------------------------------------------------------- */ /* DMA Controller */ #define DMA_BASE_WRITE (0x100) #define DMA_BASE_READ (0x140) #define DMA_CONTROL (0x00) // 64 #define DMA_ERROR (0x04) // 65 ( only read instance ) #define DMA_DIAG_CONTROL (0x1C) // 71 #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) // 72 #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) // 73 #define DMA_DIAG_TIMECOUNTER_LOW (0x28) // 74 #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) // 75 #define DMA_DIAG_RECHECKCOUNTER (0x30) // 76 ( Split completions on read ) #define DMA_DIAG_WAITTIMEOUTINIT (0x34) // 77 #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) // 78 #define DMA_DIAG_WAITCOUNTER (0x3C) // 79 // -------------------------------------------------------------------------- // DMA Buffer #define DMA_CONTROL (0x00) /* 64 */ #define DMA_ERROR (0x04) /* 65 ( only read instance ) */ #define DMA_DIAG_CONTROL (0x1C) /* 71 */ #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) /* 72 */ #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) /* 73 */ #define DMA_DIAG_TIMECOUNTER_LOW (0x28) /* 74 */ #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) /* 75 */ #define DMA_DIAG_RECHECKCOUNTER (0x30) /* 76 ( Split completions on read ) */ #define DMA_DIAG_WAITTIMEOUTINIT (0x34) /* 77 */ #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) /* 78 */ #define DMA_DIAG_WAITCOUNTER (0x3C) /* 79 */ /* ------------------------------------------------------------------------- */ /* DMA Buffer */ #define TS_INPUT_BASE (0x200) #define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) Loading drivers/media/dvb/ddbridge/ddbridge.h +4 −4 File changed.Contains only whitespace changes. Show changes Loading
drivers/media/dvb/ddbridge/ddbridge-core.c +109 −82 Original line number Diff line number Diff line Loading @@ -89,10 +89,10 @@ static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); if (stat <= 0) { printk("I2C timeout\n"); printk(KERN_ERR "I2C timeout\n"); { /* MSI debugging*/ u32 istat = ddbreadl(INTERRUPT_STATUS); printk("IRS %08x\n", istat); printk(KERN_ERR "IRS %08x\n", istat); ddbwritel(istat, INTERRUPT_ACK); } return -EIO; Loading Loading @@ -217,6 +217,7 @@ static int ddb_i2c_init(struct ddb *dev) /******************************************************************************/ /******************************************************************************/ #if 0 static void set_table(struct ddb *dev, u32 off, dma_addr_t *pbuf, u32 num) { Loading @@ -230,6 +231,7 @@ static void set_table(struct ddb *dev, u32 off, ddbwritel(mem >> 32, base + i * 8 + 4); } } #endif static void ddb_address_table(struct ddb *dev) { Loading Loading @@ -401,7 +403,7 @@ static void ddb_output_start(struct ddb_output *output) ddbwritel(1, DMA_BASE_READ); ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); //ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */ ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); output->running = 1; spin_unlock_irq(&output->lock); Loading Loading @@ -496,7 +498,7 @@ static u32 ddb_input_avail(struct ddb_input *input) off = (stat & 0x7ff) << 7; if (ctrl & 4) { printk("IA %d %d %08x\n", idx, off, ctrl); printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl); ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); return 0; } Loading Loading @@ -577,7 +579,7 @@ static int demod_attach_drxk(struct ddb_input *input) i2c, 0x29 + (input->nr&1), &input->fe2); if (!input->fe) { printk("No DRXK found!\n"); printk(KERN_ERR "No DRXK found!\n"); return -ENODEV; } fe->sec_priv = input; Loading @@ -595,7 +597,7 @@ static int tuner_attach_tda18271(struct ddb_input *input) input->fe->ops.i2c_gate_ctrl(input->fe, 1); fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); if (!fe) { printk("No TDA18271 found!\n"); printk(KERN_ERR "No TDA18271 found!\n"); return -ENODEV; } if (input->fe->ops.i2c_gate_ctrl) Loading Loading @@ -666,13 +668,13 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) (input->nr & 1) ? STV090x_DEMODULATOR_1 : STV090x_DEMODULATOR_0); if (!input->fe) { printk("No STV0900 found!\n"); printk(KERN_ERR "No STV0900 found!\n"); return -ENODEV; } if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, 0, (input->nr & 1) ? (0x09 - type) : (0x0b - type))) { printk("No LNBH24 found!\n"); printk(KERN_ERR "No LNBH24 found!\n"); return -ENODEV; } return 0; Loading @@ -688,10 +690,11 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type) ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); if (!ctl) { printk("No STV6110X found!\n"); printk(KERN_ERR "No STV6110X found!\n"); return -ENODEV; } printk("attach tuner input %d adr %02x\n", input->nr, tunerconf->addr); printk(KERN_INFO "attach tuner input %d adr %02x\n", input->nr, tunerconf->addr); feconf->tuner_init = ctl->tuner_init; feconf->tuner_sleep = ctl->tuner_sleep; Loading Loading @@ -817,7 +820,7 @@ static int dvb_input_attach(struct ddb_input *input) &input->port->dev->pdev->dev, adapter_nr); if (ret < 0) { printk("ddbridge: Could not register adapter." printk(KERN_ERR "ddbridge: Could not register adapter." "Check if you enabled enough adapters in dvb-core!\n"); return ret; } Loading Loading @@ -942,9 +945,11 @@ static ssize_t ts_read(struct file *file, char *buf, static unsigned int ts_poll(struct file *file, poll_table *wait) { /* struct dvb_device *dvbdev = file->private_data; struct ddb_output *output = dvbdev->priv; struct ddb_input *input = output->port->input[0]; */ unsigned int mask = 0; #if 0 Loading @@ -959,7 +964,7 @@ static unsigned int ts_poll(struct file *file, poll_table *wait) return mask; } static struct file_operations ci_fops = { static const struct file_operations ci_fops = { .owner = THIS_MODULE, .read = ts_read, .write = ts_write, Loading Loading @@ -995,7 +1000,7 @@ static void input_tasklet(unsigned long data) if (input->port->class == DDB_PORT_TUNER) { if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) printk("Overflow input %d\n", input->nr); printk(KERN_ERR "Overflow input %d\n", input->nr); while (input->cbuf != ((input->stat >> 11) & 0x1f) || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { dvb_dmx_swfilter_packets(&input->demux, Loading Loading @@ -1080,7 +1085,7 @@ static int ddb_port_attach(struct ddb_port *port) break; } if (ret < 0) printk("port_attach on port %d failed\n", port->nr); printk(KERN_ERR "port_attach on port %d failed\n", port->nr); return ret; } Loading Loading @@ -1132,7 +1137,7 @@ static void ddb_ports_detach(struct ddb *dev) static int port_has_ci(struct ddb_port *port) { u8 val; return (i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1); return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; } static int port_has_stv0900(struct ddb_port *port) Loading Loading @@ -1188,7 +1193,8 @@ static void ddb_port_probe(struct ddb_port *port) port->type = DDB_TUNER_DVBCT_TR; ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); } printk("Port %d (TAB %d): %s\n", port->nr, port->nr+1, modname); printk(KERN_INFO "Port %d (TAB %d): %s\n", port->nr, port->nr+1, modname); } static void ddb_input_init(struct ddb_port *port, int nr) Loading Loading @@ -1284,26 +1290,42 @@ static irqreturn_t irq_handler(int irq, void *dev_id) do { ddbwritel(s, INTERRUPT_ACK); if (s & 0x00000001) irq_handle_i2c(dev, 0); if (s & 0x00000002) irq_handle_i2c(dev, 1); if (s & 0x00000004) irq_handle_i2c(dev, 2); if (s & 0x00000008) irq_handle_i2c(dev, 3); if (s & 0x00000100) tasklet_schedule(&dev->input[0].tasklet); if (s & 0x00000200) tasklet_schedule(&dev->input[1].tasklet); if (s & 0x00000400) tasklet_schedule(&dev->input[2].tasklet); if (s & 0x00000800) tasklet_schedule(&dev->input[3].tasklet); if (s & 0x00001000) tasklet_schedule(&dev->input[4].tasklet); if (s & 0x00002000) tasklet_schedule(&dev->input[5].tasklet); if (s & 0x00004000) tasklet_schedule(&dev->input[6].tasklet); if (s & 0x00008000) tasklet_schedule(&dev->input[7].tasklet); if (s & 0x00010000) tasklet_schedule(&dev->output[0].tasklet); if (s & 0x00020000) tasklet_schedule(&dev->output[1].tasklet); if (s & 0x00040000) tasklet_schedule(&dev->output[2].tasklet); if (s & 0x00080000) tasklet_schedule(&dev->output[3].tasklet); /* if (s & 0x000f0000) printk("%08x\n", istat); */ if (s & 0x00000001) irq_handle_i2c(dev, 0); if (s & 0x00000002) irq_handle_i2c(dev, 1); if (s & 0x00000004) irq_handle_i2c(dev, 2); if (s & 0x00000008) irq_handle_i2c(dev, 3); if (s & 0x00000100) tasklet_schedule(&dev->input[0].tasklet); if (s & 0x00000200) tasklet_schedule(&dev->input[1].tasklet); if (s & 0x00000400) tasklet_schedule(&dev->input[2].tasklet); if (s & 0x00000800) tasklet_schedule(&dev->input[3].tasklet); if (s & 0x00001000) tasklet_schedule(&dev->input[4].tasklet); if (s & 0x00002000) tasklet_schedule(&dev->input[5].tasklet); if (s & 0x00004000) tasklet_schedule(&dev->input[6].tasklet); if (s & 0x00008000) tasklet_schedule(&dev->input[7].tasklet); if (s & 0x00010000) tasklet_schedule(&dev->output[0].tasklet); if (s & 0x00020000) tasklet_schedule(&dev->output[1].tasklet); if (s & 0x00040000) tasklet_schedule(&dev->output[2].tasklet); if (s & 0x00080000) tasklet_schedule(&dev->output[3].tasklet); /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ } while ((s = ddbreadl(INTERRUPT_STATUS))); return IRQ_HANDLED; Loading @@ -1325,7 +1347,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) wbuf += 4; wlen -= 4; ddbwritel(data, SPI_DATA); while (ddbreadl(SPI_CONTROL) & 0x0004); while (ddbreadl(SPI_CONTROL) & 0x0004) ; } if (rlen) Loading @@ -1344,7 +1367,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) if (shift) data <<= shift; ddbwritel(data, SPI_DATA); while (ddbreadl(SPI_CONTROL) & 0x0004); while (ddbreadl(SPI_CONTROL) & 0x0004) ; if (!rlen) { ddbwritel(0, SPI_CONTROL); Loading @@ -1355,7 +1379,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) while (rlen > 4) { ddbwritel(0xffffffff, SPI_DATA); while (ddbreadl(SPI_CONTROL) & 0x0004); while (ddbreadl(SPI_CONTROL) & 0x0004) ; data = ddbreadl(SPI_DATA); *(u32 *) rbuf = swab32(data); rbuf += 4; Loading @@ -1363,7 +1388,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) } ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); ddbwritel(0xffffffff, SPI_DATA); while (ddbreadl(SPI_CONTROL) & 0x0004); while (ddbreadl(SPI_CONTROL) & 0x0004) ; data = ddbreadl(SPI_DATA); ddbwritel(0, SPI_CONTROL); Loading Loading @@ -1421,7 +1447,7 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) if (copy_from_user(&fio, parg, sizeof(fio))) break; if (fio.write_len + fio.read_len > 1028) { printk("IOBUF too small\n"); printk(KERN_ERR "IOBUF too small\n"); return -ENOMEM; } wbuf = &dev->iobuf[0]; Loading @@ -1444,7 +1470,7 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) return res; } static struct file_operations ddb_fops={ static const struct file_operations ddb_fops = { .unlocked_ioctl = ddb_ioctl, .open = ddb_open, }; Loading @@ -1458,7 +1484,8 @@ static char *ddb_devnode(struct device *device, mode_t *mode) static int ddb_class_create(void) { if ((ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops))<0) ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); if (ddb_major < 0) return ddb_major; ddb_class = class_create(THIS_MODULE, DDB_NAME); Loading Loading @@ -1550,7 +1577,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev, dev->pdev = pdev; pci_set_drvdata(pdev, dev); dev->info = (struct ddb_info *) id->driver_data; printk("DDBridge driver detected: %s\n", dev->info->name); printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); dev->regs = ioremap(pci_resource_start(dev->pdev, 0), pci_resource_len(dev->pdev, 0)); Loading @@ -1558,7 +1585,7 @@ static int __devinit ddb_probe(struct pci_dev *pdev, stat = -ENOMEM; goto fail; } printk("HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); #ifdef CONFIG_PCI_MSI if (pci_msi_enabled()) Loading @@ -1570,9 +1597,9 @@ static int __devinit ddb_probe(struct pci_dev *pdev, dev->msi = 1; } #endif if ((stat = request_irq(dev->pdev->irq, irq_handler, irq_flag, "DDBridge", (void *) dev))<0) stat = request_irq(dev->pdev->irq, irq_handler, irq_flag, "DDBridge", (void *) dev); if (stat < 0) goto fail1; ddbwritel(0, DMA_BASE_WRITE); ddbwritel(0, DMA_BASE_READ); Loading @@ -1594,18 +1621,18 @@ static int __devinit ddb_probe(struct pci_dev *pdev, fail3: ddb_ports_detach(dev); printk("fail3\n"); printk(KERN_ERR "fail3\n"); ddb_ports_release(dev); fail2: printk("fail2\n"); printk(KERN_ERR "fail2\n"); ddb_buffers_free(dev); fail1: printk("fail1\n"); printk(KERN_ERR "fail1\n"); if (dev->msi) pci_disable_msi(dev->pdev); free_irq(dev->pdev->irq, dev); fail: printk("fail\n"); printk(KERN_ERR "fail\n"); ddb_unmap(dev); pci_set_drvdata(pdev, 0); pci_disable_device(pdev); Loading Loading @@ -1668,7 +1695,7 @@ static struct pci_driver ddb_pci_driver = { static __init int module_init_ddbridge(void) { printk("Digital Devices PCIE bridge driver, " printk(KERN_INFO "Digital Devices PCIE bridge driver, " "Copyright (C) 2010-11 Digital Devices GmbH\n"); if (ddb_class_create()) return -1; Loading
drivers/media/dvb/ddbridge/ddbridge-regs.h +31 −31 Original line number Diff line number Diff line Loading @@ -21,26 +21,26 @@ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html */ // $Id: DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred $ /* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */ // Register Definitions /* Register Definitions */ #define CUR_REGISTERMAP_VERSION 0x10000 #define HARDWARE_VERSION 0x00 #define REGISTERMAP_VERSION 0x04 // -------------------------------------------------------------------------- // SPI Controller /* ------------------------------------------------------------------------- */ /* SPI Controller */ #define SPI_CONTROL 0x10 #define SPI_DATA 0x14 // -------------------------------------------------------------------------- /* ------------------------------------------------------------------------- */ // Interrupt controller // How many MSI's are available depends on HW (Min 2 max 8) // How many are usable also depends on Host platform /* Interrupt controller */ /* How many MSI's are available depends on HW (Min 2 max 8) */ /* How many are usable also depends on Host platform */ #define INTERRUPT_BASE (0x40) Loading Loading @@ -81,15 +81,15 @@ #define INTMASK_TSOUTPUT3 (0x00040000) #define INTMASK_TSOUTPUT4 (0x00080000) // -------------------------------------------------------------------------- // I2C Master Controller /* ------------------------------------------------------------------------- */ /* I2C Master Controller */ #define I2C_BASE (0x80) // Byte offset #define I2C_BASE (0x80) /* Byte offset */ #define I2C_COMMAND (0x00) #define I2C_TIMING (0x04) #define I2C_TASKLENGTH (0x08) // High read, low write #define I2C_TASKADDRESS (0x0C) // High read, low write #define I2C_TASKLENGTH (0x08) /* High read, low write */ #define I2C_TASKADDRESS (0x0C) /* High read, low write */ #define I2C_MONITOR (0x1C) Loading @@ -100,7 +100,7 @@ #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) #define I2C_TASKMEM_BASE (0x1000) // Byte offset #define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ #define I2C_TASKMEM_SIZE (0x1000) #define I2C_SPEED_400 (0x04030404) Loading @@ -111,27 +111,27 @@ #define I2C_SPEED_50 (0x27262727) // -------------------------------------------------------------------------- // DMA Controller /* ------------------------------------------------------------------------- */ /* DMA Controller */ #define DMA_BASE_WRITE (0x100) #define DMA_BASE_READ (0x140) #define DMA_CONTROL (0x00) // 64 #define DMA_ERROR (0x04) // 65 ( only read instance ) #define DMA_DIAG_CONTROL (0x1C) // 71 #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) // 72 #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) // 73 #define DMA_DIAG_TIMECOUNTER_LOW (0x28) // 74 #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) // 75 #define DMA_DIAG_RECHECKCOUNTER (0x30) // 76 ( Split completions on read ) #define DMA_DIAG_WAITTIMEOUTINIT (0x34) // 77 #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) // 78 #define DMA_DIAG_WAITCOUNTER (0x3C) // 79 // -------------------------------------------------------------------------- // DMA Buffer #define DMA_CONTROL (0x00) /* 64 */ #define DMA_ERROR (0x04) /* 65 ( only read instance ) */ #define DMA_DIAG_CONTROL (0x1C) /* 71 */ #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) /* 72 */ #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) /* 73 */ #define DMA_DIAG_TIMECOUNTER_LOW (0x28) /* 74 */ #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) /* 75 */ #define DMA_DIAG_RECHECKCOUNTER (0x30) /* 76 ( Split completions on read ) */ #define DMA_DIAG_WAITTIMEOUTINIT (0x34) /* 77 */ #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) /* 78 */ #define DMA_DIAG_WAITCOUNTER (0x3C) /* 79 */ /* ------------------------------------------------------------------------- */ /* DMA Buffer */ #define TS_INPUT_BASE (0x200) #define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) Loading
drivers/media/dvb/ddbridge/ddbridge.h +4 −4 File changed.Contains only whitespace changes. Show changes