Commit 4d97b78a authored by Chris Morgan's avatar Chris Morgan Committed by Heiko Stuebner
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arm64: dts: rockchip: Add SFC to PX30 



Add a devicetree entry for the Rockchip SFC for the PX30 SOC.

Signed-off-by: default avatarChris Morgan <macromorgan@hotmail.com>
Signed-off-by: default avatarJon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20210812134546.31340-4-jon.lin@rock-chips.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 40b0bfbb

arch/arm64/boot/dts/rockchip/px30.dtsi

+38 −0
Original line number Diff line number Diff line
@@ -987,6 +987,18 @@ emmc: mmc@ff390000 { 
		status = "disabled";

	};



	sfc: spi@ff3a0000 {

		compatible = "rockchip,sfc";

		reg = <0x0 0xff3a0000 0x0 0x4000>;

		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;

		clock-names = "clk_sfc", "hclk_sfc";

		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;

		pinctrl-names = "default";

		power-domains = <&power PX30_PD_MMC_NAND>;

		status = "disabled";

	};



	nfc: nand-controller@ff3b0000 {

		compatible = "rockchip,px30-nfc";

		reg = <0x0 0xff3b0000 0x0 0x4000>;
@@ -2008,6 +2020,32 @@ flash_bus8: flash-bus8 { 
			};

		};



		sfc {

			sfc_bus4: sfc-bus4 {

				rockchip,pins =

					<1 RK_PA0 3 &pcfg_pull_none>,

					<1 RK_PA1 3 &pcfg_pull_none>,

					<1 RK_PA2 3 &pcfg_pull_none>,

					<1 RK_PA3 3 &pcfg_pull_none>;

			};



			sfc_bus2: sfc-bus2 {

				rockchip,pins =

					<1 RK_PA0 3 &pcfg_pull_none>,

					<1 RK_PA1 3 &pcfg_pull_none>;

			};



			sfc_cs0: sfc-cs0 {

				rockchip,pins =

					<1 RK_PA4 3 &pcfg_pull_none>;

			};



			sfc_clk: sfc-clk {

				rockchip,pins =

					<1 RK_PB1 3 &pcfg_pull_none>;

			};

		};



		lcdc {

			lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {

				rockchip,pins =