Commit 4c246408 authored by Zhen Lei's avatar Zhen Lei Committed by Wei Xu
Browse files

ARM: dts: hisilicon: fix errors detected by spi-pl022.yaml 



1. Change clock-names to "sspclk", "apb_pclk". Both of them use the same
   clock.

Signed-off-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent 05484c17

arch/arm/boot/dts/hi3519.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -127,8 +127,8 @@ spi_bus0: spi@12120000 { 
			compatible = "arm,pl022", "arm,primecell";

			reg = <0x12120000 0x1000>;

			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HI3519_SPI0_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;

			clock-names = "sspclk", "apb_pclk";

			num-cs = <1>;

			#address-cells = <1>;

			#size-cells = <0>;
@@ -139,8 +139,8 @@ spi_bus1: spi@12121000 { 
			compatible = "arm,pl022", "arm,primecell";

			reg = <0x12121000 0x1000>;

			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HI3519_SPI1_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;

			clock-names = "sspclk", "apb_pclk";

			num-cs = <1>;

			#address-cells = <1>;

			#size-cells = <0>;
@@ -151,8 +151,8 @@ spi_bus2: spi@12122000 { 
			compatible = "arm,pl022", "arm,primecell";

			reg = <0x12122000 0x1000>;

			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HI3519_SPI2_CLK>;

			clock-names = "apb_pclk";

			clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;

			clock-names = "sspclk", "apb_pclk";

			num-cs = <1>;

			#address-cells = <1>;

			#size-cells = <0>;