Commit 4c1b22a9 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Nishanth Menon
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arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node 



Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, CPSW (SGMII/QSGMII) and USB.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210105151421.23237-4-kishon@ti.com
parent edb96779

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

+63 −0
Original line number Diff line number Diff line
@@ -5,6 +5,13 @@ 
 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/

 */



/ {

	serdes_refclk: serdes-refclk {

		#clock-cells = <0>;

		compatible = "fixed-clock";

	};

};



&cbass_main {

	msmc_ram: sram@70000000 {

		compatible = "mmio-sram";
@@ -531,6 +538,62 @@ main_sdhci1: mmc@4fb0000 { 
		dma-coherent;

	};



	serdes_wiz0: wiz@5060000 {

		compatible = "ti,j721e-wiz-10g";

		#address-cells = <1>;

		#size-cells = <1>;

		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;

		clock-names = "fck", "core_ref_clk", "ext_ref_clk";

		num-lanes = <4>;

		#reset-cells = <1>;

		ranges = <0x5060000 0x0 0x5060000 0x10000>;



		assigned-clocks = <&k3_clks 292 85>;

		assigned-clock-parents = <&k3_clks 292 89>;



		wiz0_pll0_refclk: pll0-refclk {

			clocks = <&k3_clks 292 85>, <&serdes_refclk>;

			clock-output-names = "wiz0_pll0_refclk";

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_pll0_refclk>;

			assigned-clock-parents = <&k3_clks 292 85>;

		};



		wiz0_pll1_refclk: pll1-refclk {

			clocks = <&k3_clks 292 85>, <&serdes_refclk>;

			clock-output-names = "wiz0_pll1_refclk";

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_pll1_refclk>;

			assigned-clock-parents = <&k3_clks 292 85>;

		};



		wiz0_refclk_dig: refclk-dig {

			clocks = <&k3_clks 292 85>, <&serdes_refclk>;

			clock-output-names = "wiz0_refclk_dig";

			#clock-cells = <0>;

			assigned-clocks = <&wiz0_refclk_dig>;

			assigned-clock-parents = <&k3_clks 292 85>;

		};



		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {

			clocks = <&wiz0_refclk_dig>;

			#clock-cells = <0>;

		};



		serdes0: serdes@5060000 {

			compatible = "ti,j721e-serdes-10g";

			reg = <0x05060000 0x00010000>;

			reg-names = "torrent_phy";

			resets = <&serdes_wiz0 0>;

			reset-names = "torrent_reset";

			clocks = <&wiz0_pll0_refclk>;

			clock-names = "refclk";

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	usbss0: cdns-usb@4104000 {

		compatible = "ti,j721e-usb";

		reg = <0x00 0x4104000 0x00 0x100>;