Commit 4bc10d16 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu:use smc_index_11 for VI 



for VI smc, index_0 to index_8 are all not safe,
they may used by BIOS/FW, and index_11 is reserved
only for driver.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e1d99217

drivers/gpu/drm/amd/amdgpu/vi.c

+8 −8
Original line number Diff line number Diff line
@@ -121,8 +121,8 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) 
	u32 r;



	spin_lock_irqsave(&adev->smc_idx_lock, flags);

	WREG32(mmSMC_IND_INDEX_0, (reg));

	r = RREG32(mmSMC_IND_DATA_0);

	WREG32(mmSMC_IND_INDEX_11, (reg));

	r = RREG32(mmSMC_IND_DATA_11);

	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);

	return r;

}
@@ -132,8 +132,8 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 
	unsigned long flags;



	spin_lock_irqsave(&adev->smc_idx_lock, flags);

	WREG32(mmSMC_IND_INDEX_0, (reg));

	WREG32(mmSMC_IND_DATA_0, (v));

	WREG32(mmSMC_IND_INDEX_11, (reg));

	WREG32(mmSMC_IND_DATA_11, (v));

	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);

}
@@ -437,12 +437,12 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, 
	/* take the smc lock since we are using the smc index */

	spin_lock_irqsave(&adev->smc_idx_lock, flags);

	/* set rom index to 0 */

	WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);

	WREG32(mmSMC_IND_DATA_0, 0);

	WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);

	WREG32(mmSMC_IND_DATA_11, 0);

	/* set index to data for continous read */

	WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);

	WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);

	for (i = 0; i < length_dw; i++)

		dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);

		dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);

	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);



	return true;

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h

+2 −0
Original line number Diff line number Diff line
@@ -176,6 +176,8 @@ 
#define mmSMU1_SMU_SMC_IND_DATA                                                 0x83

#define mmSMU2_SMU_SMC_IND_DATA                                                 0x85

#define mmSMU3_SMU_SMC_IND_DATA                                                 0x87

#define mmSMC_IND_INDEX_11														0x1AC

#define mmSMC_IND_DATA_11														0x1AD

#define ixRCU_UC_EVENTS                                                         0xc0000004

#define ixRCU_MISC_CTRL                                                         0xc0000010

#define ixCC_RCU_FUSES                                                          0xc00c0000

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h

+2 −0
Original line number Diff line number Diff line
@@ -87,6 +87,8 @@ 
#define mmSMC_IND_DATA_6                                                        0x8d

#define mmSMC_IND_INDEX_7                                                       0x8e

#define mmSMC_IND_DATA_7                                                        0x8f

#define mmSMC_IND_INDEX_11														0x1AC

#define mmSMC_IND_DATA_11														0x1AD

#define mmSMC_IND_ACCESS_CNTL                                                   0x92

#define mmSMC_MESSAGE_0                                                         0x94

#define mmSMC_RESP_0                                                            0x95

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h

+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,8 @@ 
#define mmSMC_IND_DATA_6                                                        0x8d

#define mmSMC_IND_INDEX_7                                                       0x8e

#define mmSMC_IND_DATA_7                                                        0x8f

#define mmSMC_IND_INDEX_11														0x1AC

#define mmSMC_IND_DATA_11														0x1AD

#define mmSMC_IND_ACCESS_CNTL                                                   0x92

#define mmSMC_MESSAGE_0                                                         0x94

#define mmSMC_RESP_0                                                            0x95

drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h

+0 −2
Original line number Diff line number Diff line
@@ -28,8 +28,6 @@ 
#include <pp_endian.h>



#define SMC_RAM_END 0x40000

#define mmSMC_IND_INDEX_11                              0x01AC

#define mmSMC_IND_DATA_11                               0x01AD



struct smu7_buffer_entry {

	uint32_t data_size;