Commit 4b0b1d05 authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
Browse files

drm/amd/display: check actual clock value. 



[Why]
Actual dpp/disp clock PMFW set are always equal or more than requested.
Need to cache the actual clock for debugging purpose.

[How]
Add actuall dpp/disp clk in clock manager and save it when set clocks.
Add an ASSERT in case of actual clock less than requested.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarBindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b5fce050

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+6 −3
Original line number Diff line number Diff line
@@ -170,7 +170,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, 


	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);



		update_dispclk = true;

	}
@@ -178,10 +178,13 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, 
	if (dpp_clock_lowered) {

		// increase per DPP DTO before lowering global dppclk

		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

		clk_mgr_base->clks.actual_dppclk_khz =

				rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);



	} else {

		// increase global DPPCLK before lowering per DPP DTO

		if (update_dppclk || update_dispclk)

			clk_mgr_base->clks.actual_dppclk_khz =

					rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

		// always update dtos unless clock is lowered and not safe to lower

		if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

+8 −0
Original line number Diff line number Diff line
@@ -136,6 +136,10 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis 
		}

	}



	// pmfw always set clock more than or equal requested clock

	if (!IS_DIAG_DC(dc->ctx->dce_environment))

		ASSERT(actual_dispclk_set_mhz >= requested_dispclk_khz / 1000);



	return actual_dispclk_set_mhz * 1000;

}
@@ -194,12 +198,16 @@ void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phy 
int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

{

	int actual_dppclk_set_mhz = -1;

	struct dc *dc = clk_mgr->base.ctx->dc;



	actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(

			clk_mgr,

			VBIOSSMC_MSG_SetDppclkFreq,

			requested_dpp_khz / 1000);



	if (!IS_DIAG_DC(dc->ctx->dce_environment))

		ASSERT(actual_dppclk_set_mhz >= requested_dpp_khz / 1000);



	return actual_dppclk_set_mhz * 1000;

}

drivers/gpu/drm/amd/display/dc/dc.h

+2 −0
Original line number Diff line number Diff line
@@ -342,7 +342,9 @@ enum dcn_pwr_state { 
 */

struct dc_clocks {

	int dispclk_khz;

	int actual_dispclk_khz;

	int dppclk_khz;

	int actual_dppclk_khz;

	int disp_dpp_voltage_level_khz;

	int dcfclk_khz;

	int socclk_khz;