Commit 4984e3aa authored by Leung, Martin's avatar Leung, Martin Committed by Alex Deucher
Browse files

drm/amd/display: cleaning up smu_if to add future flexibility 



why and how:
need to hook in new smu interfaces
cleaning up code that used old variables

Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarLeung, Martin <Martin.Leung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent df5a07c4

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

+3 −10
Original line number Diff line number Diff line
@@ -25,30 +25,23 @@ 


#include "dccg.h"

#include "clk_mgr_internal.h"



#include "dcn30_clk_mgr_smu_msg.h"

#include "dcn20/dcn20_clk_mgr.h"

#include "dce100/dce_clk_mgr.h"

#include "dcn30/dcn30_clk_mgr.h"

#include "reg_helper.h"

#include "core_types.h"

#include "dm_helpers.h"



#include "atomfirmware.h"





#include "sienna_cichlid_ip_offset.h"

#include "dcn/dcn_3_0_0_offset.h"

#include "dcn/dcn_3_0_0_sh_mask.h"



#include "nbio/nbio_7_4_offset.h"



#include "dpcs/dpcs_3_0_0_offset.h"

#include "dpcs/dpcs_3_0_0_sh_mask.h"



#include "mmhub/mmhub_2_0_0_offset.h"

#include "mmhub/mmhub_2_0_0_sh_mask.h"

/*we don't have clk folder yet*/

#include "dcn30/dcn30_clk_mgr.h"

#include "dcn30_smu11_driver_if.h"



#undef FN

#define FN(reg_name, field_name) \
@@ -83,7 +76,7 @@ static const struct clk_mgr_mask clk_mgr_mask = { 




/* Query SMU for all clock states for a particular clock */

static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels)

static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)

{

	unsigned int i;

	char *entry_i = (char *)entry_0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

+5 −4
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include "clk_mgr_internal.h"

#include "reg_helper.h"

#include "dalsmc.h"

#include "dcn30_smu11_driver_if.h"



#define mmDAL_MSG_REG  0x1628A

#define mmDAL_ARG_REG  0x16273
@@ -197,7 +198,7 @@ void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) 
}



/* Returns the actual frequency that was set in MHz, 0 on failure */

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz)

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

{

	uint32_t response = 0;
@@ -215,7 +216,7 @@ unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PP 
}



/* Returns the actual frequency that was set in MHz, 0 on failure */

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz)

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

{

	uint32_t response = 0;
@@ -246,7 +247,7 @@ unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PP 
 *

 * Returns 0 on failure

 */

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint8_t dpm_level)

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

{

	uint32_t response = 0;
@@ -264,7 +265,7 @@ unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, P 
}



/* Returns the max DPM frequency in DC mode in MHz, 0 on failure */

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

{

	uint32_t response = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

+4 −63
Original line number Diff line number Diff line
@@ -28,65 +28,6 @@ 


#include "core_types.h"



#define SMU11_DRIVER_IF_VERSION 0x1F



typedef enum {

	PPCLK_GFXCLK = 0,

	PPCLK_SOCCLK,

	PPCLK_UCLK,

	PPCLK_FCLK,

	PPCLK_DCLK_0,

	PPCLK_VCLK_0,

	PPCLK_DCLK_1,

	PPCLK_VCLK_1,

	PPCLK_DCEFCLK,

	PPCLK_DISPCLK,

	PPCLK_PIXCLK,

	PPCLK_PHYCLK,

	PPCLK_DTBCLK,

	PPCLK_COUNT,

} PPCLK_e;



typedef struct {

	uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)

	uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)

	uint16_t MinUclk;

	uint16_t MaxUclk;



	uint8_t  WmSetting;

	uint8_t  Flags;

	uint8_t  Padding[2];



} WatermarkRowGeneric_t;



#define NUM_WM_RANGES 4



typedef enum {

	WM_SOCCLK = 0,

	WM_DCEFCLK,

	WM_COUNT,

} WM_CLOCK_e;



typedef enum {

	WATERMARKS_CLOCK_RANGE = 0,

	WATERMARKS_DUMMY_PSTATE,

	WATERMARKS_MALL,

	WATERMARKS_COUNT,

} WATERMARKS_FLAGS_e;



typedef struct {

	// Watermarks

	WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];

} Watermarks_t;



typedef struct {

	Watermarks_t Watermarks;



	uint32_t     MmHubPadding[8]; // SMU internal use

} WatermarksExternal_t;



#define TABLE_WATERMARKS 1



struct clk_mgr_internal;



bool         dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
@@ -97,10 +38,10 @@ void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint 
void         dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

void         dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

void         dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz);

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t freq_mhz);

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint8_t dpm_level);

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk);

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

void         dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);

void         dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);

void         dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h

0 → 100644
+74 −0
Original line number Diff line number Diff line 
// This is a stripped-down version of the smu11_driver_if.h file for the relevant DAL interfaces.



#define SMU11_DRIVER_IF_VERSION 0x40



//Only Clks that have DPM descriptors are listed here

typedef enum {

	PPCLK_GFXCLK = 0,

	PPCLK_SOCCLK,

	PPCLK_UCLK,

	PPCLK_FCLK,

	PPCLK_DCLK_0,

	PPCLK_VCLK_0,

	PPCLK_DCLK_1,

	PPCLK_VCLK_1,

	PPCLK_DCEFCLK,

	PPCLK_DISPCLK,

	PPCLK_PIXCLK,

	PPCLK_PHYCLK,

	PPCLK_DTBCLK,

	PPCLK_COUNT,

} PPCLK_e;



typedef struct {

	uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)

	uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)

	uint16_t MinUclk;

	uint16_t MaxUclk;



	uint8_t  WmSetting;

	uint8_t  Flags;

	uint8_t  Padding[2];



} WatermarkRowGeneric_t;



#define NUM_WM_RANGES 4



typedef enum {

	WM_SOCCLK = 0,

	WM_DCEFCLK,

	WM_COUNT,

} WM_CLOCK_e;



typedef enum {

	WATERMARKS_CLOCK_RANGE = 0,

	WATERMARKS_DUMMY_PSTATE,

	WATERMARKS_MALL,

	WATERMARKS_COUNT,

} WATERMARKS_FLAGS_e;



typedef struct {

	// Watermarks

	WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];

} Watermarks_t;



typedef struct {

	Watermarks_t Watermarks;



	uint32_t     MmHubPadding[8]; // SMU internal use

} WatermarksExternal_t;



// Table types

#define TABLE_PPTABLE                 0

#define TABLE_WATERMARKS              1

#define TABLE_AVFS_PSM_DEBUG          2

#define TABLE_AVFS_FUSE_OVERRIDE      3

#define TABLE_PMSTATUSLOG             4

#define TABLE_SMU_METRICS             5

#define TABLE_DRIVER_SMU_CONFIG       6

#define TABLE_ACTIVITY_MONITOR_COEFF  7

#define TABLE_OVERDRIVE               8

#define TABLE_I2C_COMMANDS            9

#define TABLE_PACE                   10

#define TABLE_ECCINFO                11

#define TABLE_COUNT                  12

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

+0 −22
Original line number Diff line number Diff line
@@ -419,28 +419,6 @@ struct integrated_info { 
	struct edp_info edp2_info;

};



/**

* Power source ids.

*/

enum power_source {

	POWER_SOURCE_AC = 0,

	POWER_SOURCE_DC,

	POWER_SOURCE_LIMITED_POWER,

	POWER_SOURCE_LIMITED_POWER_2,

	POWER_SOURCE_MAX

};



struct bios_event_info {

	uint32_t thermal_state;

	uint32_t backlight_level;

	enum power_source powerSource;

	bool has_thermal_state_changed;

	bool has_power_source_changed;

	bool has_forced_mode_changed;

	bool forced_mode;

	bool backlight_changed;

};



/*

 * DFS-bypass flag

 */