Commit 49070c4e authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: split umc callbacks to ras and non-ras ones 



umc ras is not managed by gpu driver when gpu is
connected to cpu through xgmi. split umc callbacks
into ras and non-ras ones so gpu driver only
initializes umc ras callbacks when it manages
umc ras.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarDennis Li <Dennis.Li@amd.com>
Reviewed-by: default avatarJohn Clements <John.Clements@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 52137ca8

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+8 −3
Original line number Diff line number Diff line
@@ -391,8 +391,9 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 
{

	int r;



	if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {

		r = adev->umc.funcs->ras_late_init(adev);

	if (adev->umc.ras_funcs &&

	    adev->umc.ras_funcs->ras_late_init) {

		r = adev->umc.ras_funcs->ras_late_init(adev);

		if (r)

			return r;

	}
@@ -418,8 +419,12 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 


void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)

{

	amdgpu_umc_ras_fini(adev);

	if (adev->umc.ras_funcs &&

	    adev->umc.ras_funcs->ras_fini)

		adev->umc.ras_funcs->ras_fini(adev);



	amdgpu_mmhub_ras_fini(adev);



	if (adev->gmc.xgmi.ras_funcs &&

	    adev->gmc.xgmi.ras_funcs->ras_fini)

		adev->gmc.xgmi.ras_funcs->ras_fini(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+6 −4
Original line number Diff line number Diff line
@@ -774,13 +774,15 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 


	switch (info->head.block) {

	case AMDGPU_RAS_BLOCK__UMC:

		if (adev->umc.funcs->query_ras_error_count)

			adev->umc.funcs->query_ras_error_count(adev, &err_data);

		if (adev->umc.ras_funcs &&

		    adev->umc.ras_funcs->query_ras_error_count)

			adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);

		/* umc query_ras_error_address is also responsible for clearing

		 * error status

		 */

		if (adev->umc.funcs->query_ras_error_address)

			adev->umc.funcs->query_ras_error_address(adev, &err_data);

		if (adev->umc.ras_funcs &&

		    adev->umc.ras_funcs->query_ras_error_address)

			adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);

		break;

	case AMDGPU_RAS_BLOCK__SDMA:

		if (adev->sdma.funcs->query_ras_error_count) {

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c

+9 −8
Original line number Diff line number Diff line
@@ -60,8 +60,9 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev) 
	}



	/* ras init of specific umc version */

	if (adev->umc.funcs && adev->umc.funcs->err_cnt_init)

		adev->umc.funcs->err_cnt_init(adev);

	if (adev->umc.ras_funcs &&

	    adev->umc.ras_funcs->err_cnt_init)

		adev->umc.ras_funcs->err_cnt_init(adev);



	return 0;
@@ -95,12 +96,12 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 
	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;



	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);

	if (adev->umc.funcs &&

	    adev->umc.funcs->query_ras_error_count)

	    adev->umc.funcs->query_ras_error_count(adev, ras_error_status);

	if (adev->umc.ras_funcs &&

	    adev->umc.ras_funcs->query_ras_error_count)

	    adev->umc.ras_funcs->query_ras_error_count(adev, ras_error_status);



	if (adev->umc.funcs &&

	    adev->umc.funcs->query_ras_error_address &&

	if (adev->umc.ras_funcs &&

	    adev->umc.ras_funcs->query_ras_error_address &&

	    adev->umc.max_ras_err_cnt_per_query) {

		err_data->err_addr =

			kcalloc(adev->umc.max_ras_err_cnt_per_query,
@@ -116,7 +117,7 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 
		/* umc query_ras_error_address is also responsible for clearing

		 * error status

		 */

		adev->umc.funcs->query_ras_error_address(adev, ras_error_status);

		adev->umc.ras_funcs->query_ras_error_address(adev, ras_error_status);

	}



	/* only uncorrectable error needs gpu reset */

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

+7 −2
Original line number Diff line number Diff line
@@ -35,13 +35,17 @@ 
#define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)

#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))



struct amdgpu_umc_funcs {

struct amdgpu_umc_ras_funcs {

	void (*err_cnt_init)(struct amdgpu_device *adev);

	int (*ras_late_init)(struct amdgpu_device *adev);

	void (*ras_fini)(struct amdgpu_device *adev);

	void (*query_ras_error_count)(struct amdgpu_device *adev,

				      void *ras_error_status);

	void (*query_ras_error_address)(struct amdgpu_device *adev,

					void *ras_error_status);

};



struct amdgpu_umc_funcs {

	void (*init_registers)(struct amdgpu_device *adev);

};
@@ -59,6 +63,7 @@ struct amdgpu_umc { 
	struct ras_common_if *ras_if;



	const struct amdgpu_umc_funcs *funcs;

	const struct amdgpu_umc_ras_funcs *ras_funcs;

};



int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+1 −1
Original line number Diff line number Diff line
@@ -655,7 +655,7 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 
		adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;

		adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;

		adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];

		adev->umc.funcs = &umc_v8_7_funcs;

		adev->umc.ras_funcs = &umc_v8_7_ras_funcs;

		break;

	default:

		break;