Commit 44a99b65 authored by Andrey Grodzovsky's avatar Andrey Grodzovsky Committed by Alex Deucher
Browse files

drm/amd: Use newly added interrupt source defs for SOC15. 



Signed-off-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ba61bb17

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+6 −4
Original line number Diff line number Diff line
@@ -38,6 +38,8 @@ 
#include "clearstate_gfx9.h"

#include "v9_structs.h"



#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"



#define GFX9_NUM_GFX_RINGS     1

#define GFX9_MEC_HPD_SIZE 2048

#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@@ -1488,23 +1490,23 @@ static int gfx_v9_0_sw_init(void *handle) 
	adev->gfx.mec.num_queue_per_pipe = 8;



	/* KIQ event */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT, &adev->gfx.kiq.irq);

	if (r)

		return r;



	/* EOP Event */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);

	if (r)

		return r;



	/* Privileged reg */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,

			      &adev->gfx.priv_reg_irq);

	if (r)

		return r;



	/* Privileged inst */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,

			      &adev->gfx.priv_inst_irq);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+4 −2
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ 
#include "gfxhub_v1_0.h"

#include "mmhub_v1_0.h"



#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"



/* add these here since we already include dce12 headers and these are for DCN */

#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d

#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
@@ -877,9 +879,9 @@ static int gmc_v9_0_sw_init(void *handle) 
	}



	/* This interrupt is VMC page fault.*/

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 0,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,

				&adev->gmc.vm_fault);

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 0,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,

				&adev->gmc.vm_fault);



	if (r)

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+5 −2
Original line number Diff line number Diff line
@@ -38,6 +38,9 @@ 
#include "soc15.h"

#include "vega10_sdma_pkt_open.h"



#include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"

#include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"



MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");

MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");

MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
@@ -1225,13 +1228,13 @@ static int sdma_v4_0_sw_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	/* SDMA trap event */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP,

			      &adev->sdma.trap_irq);

	if (r)

		return r;



	/* SDMA trap event */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224,

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP,

			      &adev->sdma.trap_irq);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

+3 −2
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#include "hdp/hdp_4_0_offset.h"

#include "mmhub/mmhub_1_0_offset.h"

#include "mmhub/mmhub_1_0_sh_mask.h"

#include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"



#define UVD7_MAX_HW_INSTANCES_VEGA20			2
@@ -402,13 +403,13 @@ static int uvd_v7_0_sw_init(void *handle) 


	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {

		/* UVD TRAP */

		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], 124, &adev->uvd.inst[j].irq);

		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);

		if (r)

			return r;



		/* UVD ENC TRAP */

		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {

			r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + 119, &adev->uvd.inst[j].irq);

			r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);

			if (r)

				return r;

		}

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

+2 −0
Original line number Diff line number Diff line
@@ -39,6 +39,8 @@ 
#include "mmhub/mmhub_1_0_offset.h"

#include "mmhub/mmhub_1_0_sh_mask.h"



#include "ivsrcid/vce/irqsrcs_vce_4_0.h"



#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK	0x02



#define VCE_V4_0_FW_SIZE	(384 * 1024)