Commit 439a95a0 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'dt-schema-5.10' of... 

Merge tag 'dt-schema-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Various minor cleanups for ARM DTS

Cleanup ARM DTS to remove dtschema validation errors.

* tag 'dt-schema-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: alpine: Align GIC nodename with dtschema
  ARM: dts: zx: Align L2 cache-controller nodename with dtschema
  ARM: dts: tango: Align L2 cache-controller nodename with dtschema
  ARM: dts: spear: Align L2 cache-controller nodename with dtschema
  ARM: dts: qcom: Align L2 cache-controller nodename with dtschema
  ARM: dts: prima: Align L2 cache-controller nodename with dtschema

Link: https://lore.kernel.org/r/20200911155509.1495-2-krzk@kernel.org


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents b5ac61e4 48d5732c

arch/arm/boot/dts/alpine.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ arch-timer { 
		};



		/* Interrupt Controller */

		gic: gic@fb001000 {

		gic: interrupt-controller@fb001000 {

			compatible = "arm,cortex-a15-gic";

			#interrupt-cells = <3>;

			#size-cells = <0>;

arch/arm/boot/dts/prima2.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ axi { 
		#size-cells = <1>;

		ranges = <0x40000000 0x40000000 0x80000000>;



		l2-cache-controller@80040000 {

		cache-controller@80040000 {

			compatible = "arm,pl310-cache";

			reg = <0x80040000 0x1000>;

			interrupts = <59>;

arch/arm/boot/dts/qcom-mdm9615.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ soc: soc { 
		ranges;

		compatible = "simple-bus";



		L2: l2-cache@2040000 {

		L2: cache-controller@2040000 {

			compatible = "arm,pl310-cache";

			reg = <0x02040000 0x1000>;

			arm,data-latency = <2 2 0>;

arch/arm/boot/dts/spear13xx.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ pmu { 
			      0 7 0x04>;

	};



	L2: l2-cache {

	L2: cache-controller {

		    compatible = "arm,pl310-cache";

		    reg = <0xed000000 0x1000>;

		    cache-unified;

arch/arm/boot/dts/tango4-common.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ gic: interrupt-controller@1000 { 
		};

	};



	l2cc: l2-cache-controller@20100000 {

	l2cc: cache-controller@20100000 {

		compatible = "arm,pl310-cache";

		reg = <0x20100000 0x1000>;

		cache-level = <2>;