Loading arch/x86/kernel/apic_32.c +2 −2 Original line number Diff line number Diff line Loading @@ -135,9 +135,9 @@ void apic_wait_icr_idle(void) cpu_relax(); } unsigned long safe_apic_wait_icr_idle(void) u32 safe_apic_wait_icr_idle(void) { unsigned long send_status; u32 send_status; int timeout; timeout = 0; Loading arch/x86/lguest/boot.c +2 −2 Original line number Diff line number Diff line Loading @@ -788,11 +788,11 @@ static void lguest_wbinvd(void) * code qualifies for Advanced. It will also never interrupt anything. It * does, however, allow us to get through the Linux boot code. */ #ifdef CONFIG_X86_LOCAL_APIC static void lguest_apic_write(unsigned long reg, unsigned long v) static void lguest_apic_write(unsigned long reg, u32 v) { } static unsigned long lguest_apic_read(unsigned long reg) static u32 lguest_apic_read(unsigned long reg) { return 0; } Loading arch/x86/xen/enlighten.c +2 −2 Original line number Diff line number Diff line Loading @@ -521,12 +521,12 @@ static void xen_io_delay(void) } #ifdef CONFIG_X86_LOCAL_APIC static unsigned long xen_apic_read(unsigned long reg) static u32 xen_apic_read(unsigned long reg) { return 0; } static void xen_apic_write(unsigned long reg, unsigned long val) static void xen_apic_write(unsigned long reg, u32 val) { /* Warn to see if there's any stray references */ WARN_ON(1); Loading include/asm-x86/apic_32.h +7 −9 Original line number Diff line number Diff line Loading @@ -51,25 +51,23 @@ extern int local_apic_timer_disabled; #define setup_secondary_clock setup_secondary_APIC_clock #endif static __inline fastcall void native_apic_write(unsigned long reg, unsigned long v) static __inline fastcall void native_apic_write(unsigned long reg, u32 v) { *((volatile unsigned long *)(APIC_BASE+reg)) = v; *((volatile u32 *)(APIC_BASE + reg)) = v; } static __inline fastcall void native_apic_write_atomic(unsigned long reg, unsigned long v) static __inline fastcall void native_apic_write_atomic(unsigned long reg, u32 v) { xchg((volatile unsigned long *)(APIC_BASE+reg), v); (void) xchg((u32 *)(APIC_BASE + reg), v); } static __inline fastcall unsigned long native_apic_read(unsigned long reg) static __inline fastcall u32 native_apic_read(unsigned long reg) { return *((volatile unsigned long *)(APIC_BASE+reg)); return *((volatile u32 *)(APIC_BASE + reg)); } extern void apic_wait_icr_idle(void); extern unsigned long safe_apic_wait_icr_idle(void); extern u32 safe_apic_wait_icr_idle(void); extern int get_physical_broadcast(void); #ifdef CONFIG_X86_GOOD_APIC Loading include/asm-x86/apic_64.h +3 −3 Original line number Diff line number Diff line Loading @@ -38,14 +38,14 @@ struct pt_regs; * Basic functions accessing APICs. */ static __inline void apic_write(unsigned long reg, unsigned int v) static __inline void apic_write(unsigned long reg, u32 v) { *((volatile unsigned int *)(APIC_BASE+reg)) = v; } static __inline unsigned int apic_read(unsigned long reg) static __inline u32 apic_read(unsigned long reg) { return *((volatile unsigned int *)(APIC_BASE+reg)); return *((volatile u32 *)(APIC_BASE+reg)); } extern void apic_wait_icr_idle(void); Loading Loading
arch/x86/kernel/apic_32.c +2 −2 Original line number Diff line number Diff line Loading @@ -135,9 +135,9 @@ void apic_wait_icr_idle(void) cpu_relax(); } unsigned long safe_apic_wait_icr_idle(void) u32 safe_apic_wait_icr_idle(void) { unsigned long send_status; u32 send_status; int timeout; timeout = 0; Loading
arch/x86/lguest/boot.c +2 −2 Original line number Diff line number Diff line Loading @@ -788,11 +788,11 @@ static void lguest_wbinvd(void) * code qualifies for Advanced. It will also never interrupt anything. It * does, however, allow us to get through the Linux boot code. */ #ifdef CONFIG_X86_LOCAL_APIC static void lguest_apic_write(unsigned long reg, unsigned long v) static void lguest_apic_write(unsigned long reg, u32 v) { } static unsigned long lguest_apic_read(unsigned long reg) static u32 lguest_apic_read(unsigned long reg) { return 0; } Loading
arch/x86/xen/enlighten.c +2 −2 Original line number Diff line number Diff line Loading @@ -521,12 +521,12 @@ static void xen_io_delay(void) } #ifdef CONFIG_X86_LOCAL_APIC static unsigned long xen_apic_read(unsigned long reg) static u32 xen_apic_read(unsigned long reg) { return 0; } static void xen_apic_write(unsigned long reg, unsigned long val) static void xen_apic_write(unsigned long reg, u32 val) { /* Warn to see if there's any stray references */ WARN_ON(1); Loading
include/asm-x86/apic_32.h +7 −9 Original line number Diff line number Diff line Loading @@ -51,25 +51,23 @@ extern int local_apic_timer_disabled; #define setup_secondary_clock setup_secondary_APIC_clock #endif static __inline fastcall void native_apic_write(unsigned long reg, unsigned long v) static __inline fastcall void native_apic_write(unsigned long reg, u32 v) { *((volatile unsigned long *)(APIC_BASE+reg)) = v; *((volatile u32 *)(APIC_BASE + reg)) = v; } static __inline fastcall void native_apic_write_atomic(unsigned long reg, unsigned long v) static __inline fastcall void native_apic_write_atomic(unsigned long reg, u32 v) { xchg((volatile unsigned long *)(APIC_BASE+reg), v); (void) xchg((u32 *)(APIC_BASE + reg), v); } static __inline fastcall unsigned long native_apic_read(unsigned long reg) static __inline fastcall u32 native_apic_read(unsigned long reg) { return *((volatile unsigned long *)(APIC_BASE+reg)); return *((volatile u32 *)(APIC_BASE + reg)); } extern void apic_wait_icr_idle(void); extern unsigned long safe_apic_wait_icr_idle(void); extern u32 safe_apic_wait_icr_idle(void); extern int get_physical_broadcast(void); #ifdef CONFIG_X86_GOOD_APIC Loading
include/asm-x86/apic_64.h +3 −3 Original line number Diff line number Diff line Loading @@ -38,14 +38,14 @@ struct pt_regs; * Basic functions accessing APICs. */ static __inline void apic_write(unsigned long reg, unsigned int v) static __inline void apic_write(unsigned long reg, u32 v) { *((volatile unsigned int *)(APIC_BASE+reg)) = v; } static __inline unsigned int apic_read(unsigned long reg) static __inline u32 apic_read(unsigned long reg) { return *((volatile unsigned int *)(APIC_BASE+reg)); return *((volatile u32 *)(APIC_BASE+reg)); } extern void apic_wait_icr_idle(void); Loading