Commit 428f6882 authored by Benjamin Dotan's avatar Benjamin Dotan Committed by Oded Gabbay
Browse files

accel/habanalabs: fix ETR/ETF flush logic 



When config_etr or config_etf are called we need to validate the
parameters that are passed into them to make sure the requested
operation is valid.

Signed-off-by: default avatarBenjamin Dotan <bdotan@habana.ai>
Reviewed-by: default avatarOded Gabbay <ogabbay@kernel.org>
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent cf1ed52d

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

+12 −0
Original line number Diff line number Diff line
@@ -482,6 +482,11 @@ static int gaudi_config_etf(struct hl_device *hdev, 


	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);



	val = RREG32(base_reg + 0x20);



	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))

		return 0;



	val = RREG32(base_reg + 0x304);

	val |= 0x1000;

	WREG32(base_reg + 0x304, val);
@@ -580,6 +585,13 @@ static int gaudi_config_etr(struct hl_device *hdev, 


	WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);



	val = RREG32(mmPSOC_ETR_CTL);



	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))

		return 0;







	val = RREG32(mmPSOC_ETR_FFCR);

	val |= 0x1000;

	WREG32(mmPSOC_ETR_FFCR, val);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

+10 −0
Original line number Diff line number Diff line
@@ -2092,6 +2092,11 @@ static int gaudi2_config_etf(struct hl_device *hdev, struct hl_debug_params *par 
	if (rc)

		return -EIO;



	val = RREG32(base_reg + mmETF_CTL_OFFSET);



	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))

		return 0;



	val = RREG32(base_reg + mmETF_FFCR_OFFSET);

	val |= 0x1000;

	WREG32(base_reg + mmETF_FFCR_OFFSET, val);
@@ -2189,6 +2194,11 @@ static int gaudi2_config_etr(struct hl_device *hdev, struct hl_ctx *ctx, 
	if (rc)

		return -EIO;



	val = RREG32(mmPSOC_ETR_CTL);



	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))

		return 0;



	val = RREG32(mmPSOC_ETR_FFCR);

	val |= 0x1000;

	WREG32(mmPSOC_ETR_FFCR, val);

drivers/accel/habanalabs/goya/goya_coresight.c

+10 −0
Original line number Diff line number Diff line
@@ -315,6 +315,11 @@ static int goya_config_etf(struct hl_device *hdev, 


	WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);



	val = RREG32(base_reg + 0x20);



	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))

		return 0;



	val = RREG32(base_reg + 0x304);

	val |= 0x1000;

	WREG32(base_reg + 0x304, val);
@@ -386,6 +391,11 @@ static int goya_config_etr(struct hl_device *hdev, 


	WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);



	val = RREG32(mmPSOC_ETR_CTL);



	if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))

		return 0;



	val = RREG32(mmPSOC_ETR_FFCR);

	val |= 0x1000;

	WREG32(mmPSOC_ETR_FFCR, val);