ice: prefix clock timer command enumeration values with ICE_PTP

	cmd_val = tmr_idx << SEL_CPK_SRC;

	switch (cmd) {

	case INIT_TIME:

	case ICE_PTP_INIT_TIME:

		cmd_val |= GLTSYN_CMD_INIT_TIME;

		break;

	case INIT_INCVAL:

	case ICE_PTP_INIT_INCVAL:

		cmd_val |= GLTSYN_CMD_INIT_INCVAL;

		break;

	case ADJ_TIME:

	case ICE_PTP_ADJ_TIME:

		cmd_val |= GLTSYN_CMD_ADJ_TIME;

		break;

	case ADJ_TIME_AT_TIME:

	case ICE_PTP_ADJ_TIME_AT_TIME:

		cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;

		break;

	case READ_TIME:

	case ICE_PTP_READ_TIME:

		cmd_val |= GLTSYN_CMD_READ_TIME;

		break;

	case ICE_PTP_NOP:

 * @time: Time to initialize the PHY port clocks to

 *

 * Program the PHY port registers with a new initial time value. The port

 * clock will be initialized once the driver issues an INIT_TIME sync

 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync

 * command. The time value is the upper 32 bits of the PHY timer, usually in

 * units of nominal nanoseconds.

 */

 *

 * Program the port for an atomic adjustment by writing the Tx and Rx timer

 * registers. The atomic adjustment won't be completed until the driver issues

 * an ADJ_TIME command.

 * an ICE_PTP_ADJ_TIME command.

 *

 * Note that time is not in units of nanoseconds. It is in clock time

 * including the lower sub-nanosecond portion of the port timer.

 *

 * Prepare the PHY ports for an atomic time adjustment by programming the PHY

 * Tx and Rx port registers. The actual adjustment is completed by issuing an

 * ADJ_TIME or ADJ_TIME_AT_TIME sync command.

 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.

 */

static int

ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj)

 *

 * Prepare each of the PHY ports for a new increment value by programming the

 * port's TIMETUS registers. The new increment value will be updated after

 * issuing an INIT_INCVAL command.

 * issuing an ICE_PTP_INIT_INCVAL command.

 */

static int

ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)

	tmr_idx = ice_get_ptp_src_clock_index(hw);

	cmd_val = tmr_idx << SEL_PHY_SRC;

	switch (cmd) {

	case INIT_TIME:

	case ICE_PTP_INIT_TIME:

		cmd_val |= PHY_CMD_INIT_TIME;

		break;

	case INIT_INCVAL:

	case ICE_PTP_INIT_INCVAL:

		cmd_val |= PHY_CMD_INIT_INCVAL;

		break;

	case ADJ_TIME:

	case ICE_PTP_ADJ_TIME:

		cmd_val |= PHY_CMD_ADJ_TIME;

		break;

	case READ_TIME:

	case ICE_PTP_READ_TIME:

		cmd_val |= PHY_CMD_READ_TIME;

		break;

	case ADJ_TIME_AT_TIME:

	case ICE_PTP_ADJ_TIME_AT_TIME:

		cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;

		break;

	case ICE_PTP_NOP:

 * @phy_time: on return, the 64bit PHY timer value

 * @phc_time: on return, the lower 64bits of PHC time

 *

 * Issue a READ_TIME timer command to simultaneously capture the PHY and PHC

 * timer values.

 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY

 * and PHC timer values.

 */

static int

ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,

	tmr_idx = ice_get_ptp_src_clock_index(hw);

	/* Prepare the PHC timer for a READ_TIME capture command */

	ice_ptp_src_cmd(hw, READ_TIME);

	/* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */

	ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);

	/* Prepare the PHY timer for a READ_TIME capture command */

	err = ice_ptp_one_port_cmd(hw, port, READ_TIME);

	/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */

	err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);

	if (err)

		return err;

	/* Issue the sync to start the READ_TIME capture */

	/* Issue the sync to start the ICE_PTP_READ_TIME capture */

	ice_ptp_exec_tmr_cmd(hw);

	/* Read the captured PHC time from the shadow time registers */

 * @port: the PHY port to synchronize

 *

 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.

 * This is done by issuing a READ_TIME command which triggers a simultaneous

 * read of the PHY timer and PHC timer. Then we use the difference to

 * calculate an appropriate 2s complement addition to add to the PHY timer in

 * order to ensure it reads the same value as the primary PHC timer.

 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a

 * simultaneous read of the PHY timer and PHC timer. Then we use the

 * difference to calculate an appropriate 2s complement addition to add

 * to the PHY timer in order to ensure it reads the same value as the

 * primary PHC timer.

 */

static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)

{

	if (err)

		goto err_unlock;

	err = ice_ptp_one_port_cmd(hw, port, ADJ_TIME);

	err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);

	if (err)

		goto err_unlock;

	if (err)

		return err;

	err = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL);

	err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);

	if (err)

		return err;

	if (err)

		return err;

	err = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL);

	err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);

	if (err)

		return err;

 *

 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the

 * initial clock time. The time will not actually be programmed until the

 * driver issues an INIT_TIME command.

 * driver issues an ICE_PTP_INIT_TIME command.

 *

 * The time value is the upper 32 bits of the PHY timer, usually in units of

 * nominal nanoseconds.

 *

 * Prepare the PHY port for an atomic adjustment by programming the PHY

 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment

 * is completed by issuing an ADJ_TIME sync command.

 * is completed by issuing an ICE_PTP_ADJ_TIME sync command.

 *

 * The adjustment value only contains the portion used for the upper 32bits of

 * the PHY timer, usually in units of nominal nanoseconds. Negative

 *

 * Prepare the PHY port for a new increment value by programming the PHY

 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is

 * completed by issuing an INIT_INCVAL command.

 * completed by issuing an ICE_PTP_INIT_INCVAL command.

 */

static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)

{

	int err;

	switch (cmd) {

	case INIT_TIME:

	case ICE_PTP_INIT_TIME:

		cmd_val = GLTSYN_CMD_INIT_TIME;

		break;

	case INIT_INCVAL:

	case ICE_PTP_INIT_INCVAL:

		cmd_val = GLTSYN_CMD_INIT_INCVAL;

		break;

	case ADJ_TIME:

	case ICE_PTP_ADJ_TIME:

		cmd_val = GLTSYN_CMD_ADJ_TIME;

		break;

	case READ_TIME:

	case ICE_PTP_READ_TIME:

		cmd_val = GLTSYN_CMD_READ_TIME;

		break;

	case ADJ_TIME_AT_TIME:

	case ICE_PTP_ADJ_TIME_AT_TIME:

		cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;

		break;

	case ICE_PTP_NOP:

	if (err)

		return err;

	return ice_ptp_tmr_cmd(hw, INIT_TIME);

	return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME);

}

/**

 *

 * 1) Write the increment value to the source timer shadow registers

 * 2) Write the increment value to the PHY timer shadow registers

 * 3) Issue an INIT_INCVAL timer command to synchronously switch both the

 *    source and port timers to the new increment value at the next clock

 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both

 *    the source and port timers to the new increment value at the next clock

 *    cycle.

 */

int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)

	if (err)

		return err;

	return ice_ptp_tmr_cmd(hw, INIT_INCVAL);

	return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL);

}

/**

 *

 * 1) Write the adjustment to the source timer shadow registers

 * 2) Write the adjustment to the PHY timer shadow registers

 * 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to

 *    both the source and port timers at the next clock cycle.

 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the

 *    adjustment to both the source and port timers at the next clock cycle.

 */

int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)

{

	tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;

	/* Write the desired clock adjustment into the GLTSYN_SHADJ register.

	 * For an ADJ_TIME command, this set of registers represents the value

	 * to add to the clock time. It supports subtraction by interpreting

	 * the value as a 2's complement integer.

	 * For an ICE_PTP_ADJ_TIME command, this set of registers represents

	 * the value to add to the clock time. It supports subtraction by

	 * interpreting the value as a 2's complement integer.

	 */

	wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);

	wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);

	if (err)

		return err;

	return ice_ptp_tmr_cmd(hw, ADJ_TIME);

	return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME);

}

/**

#include <linux/dpll.h>

enum ice_ptp_tmr_cmd {

	INIT_TIME,

	INIT_INCVAL,

	ADJ_TIME,

	ADJ_TIME_AT_TIME,

	READ_TIME,

	ICE_PTP_INIT_TIME,

	ICE_PTP_INIT_INCVAL,

	ICE_PTP_ADJ_TIME,

	ICE_PTP_ADJ_TIME_AT_TIME,

	ICE_PTP_READ_TIME,

	ICE_PTP_NOP,

};