Commit 3f6dba70 authored by Simon Horman's avatar Simon Horman
Browse files

ARM: dts: r8a7779: Remove unnecessary clock-output-names properties 



* Fixed rate and fixed factor clocks do not require an
  clock-output-names property.
* Since 07705583 ("clk: shmobile: div6: Make clock-output-names
  optional") Renesas div6 clocks do not require a clock-output-names
  property.

In the above cases there is only one clock output and its name is taken
from that of the clock node.  Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.

Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 452fc899

arch/arm/boot/dts/r8a7779.dtsi

+5 −10
Original line number Diff line number Diff line
@@ -445,12 +445,11 @@ clocks { 
		ranges;



		/* External root clock */

		extal_clk: extal_clk {

		extal_clk: extal {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			/* This value must be overriden by the board. */

			clock-frequency = <0>;

			clock-output-names = "extal";

		};



		/* External SCIF clock */
@@ -474,37 +473,33 @@ cpg_clocks: clocks@ffc80000 { 
		};



		/* Fixed factor clocks */

		i_clk: i_clk {

		i_clk: i {

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;

			#clock-cells = <0>;

			clock-div = <2>;

			clock-mult = <1>;

			clock-output-names = "i";

		};

		s3_clk: s3_clk {

		s3_clk: s3 {

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;

			#clock-cells = <0>;

			clock-div = <8>;

			clock-mult = <1>;

			clock-output-names = "s3";

		};

		s4_clk: s4_clk {

		s4_clk: s4 {

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;

			#clock-cells = <0>;

			clock-div = <16>;

			clock-mult = <1>;

			clock-output-names = "s4";

		};

		g_clk: g_clk {

		g_clk: g {

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;

			#clock-cells = <0>;

			clock-div = <24>;

			clock-mult = <1>;

			clock-output-names = "g";

		};



		/* Gate clocks */