Commit 3f02c6a8 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-5.11-dt-bindings' of... 

Merge tag 'tegra-for-5.11-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v5.11-rc1

This contains a couple of conversions of bindings to json-schema, as
well as symbolic names for the various memory clients on Tegra20,
Tegra30 and Tegra124. There's also a couple of fixes for Tegra194
pinmux and ARM GIC bindings. Finally, a new vendor prefix is added
for Ouya and the Ouya game console compatible string is defined.

* tag 'tegra-for-5.11-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: bus: Convert ACONNECT doc to json-schema
  dt-bindings: interrupt-controller: arm,gic: Update Tegra compatibles
  dt-bindings: dma: Convert ADMA doc to json-schema
  dt-bindings: Fix entry name for I/O High Voltage property
  dt-bindings: ARM: tegra: Add Ouya game console
  dt-bindings: Add vendor prefix for Ouya Inc.
  dt-bindings: memory: tegra124: Add memory client IDs
  dt-bindings: memory: tegra30: Add memory client IDs
  dt-bindings: memory: tegra20: Add memory client IDs

Link: https://lore.kernel.org/r/20201127144329.124891-1-thierry.reding@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents eb149c92 e36f9381

Documentation/devicetree/bindings/arm/tegra.yaml

+3 −0
Original line number Diff line number Diff line
@@ -71,6 +71,9 @@ properties: 
          - const: asus,tilapia

          - const: asus,grouper

          - const: nvidia,tegra30

      - items:

          - const: ouya,ouya

          - const: nvidia,tegra30

      - items:

          - enum:

              - nvidia,dalmore

Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt

deleted100644 → 0
+0 −44
Original line number Diff line number Diff line 
NVIDIA Tegra ACONNECT Bus



The Tegra ACONNECT bus is an AXI switch which is used to connnect various

components inside the Audio Processing Engine (APE). All CPU accesses to

the APE subsystem go through the ACONNECT via an APB to AXI wrapper.



Required properties:

- compatible: Must be "nvidia,tegra210-aconnect".

- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),

  and APE interface clock (TEGRA210_CLK_APB2APE).

- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding

  'clocks' entries.

- power-domains: Must contain a phandle that points to the audio powergate

  (namely 'aud') for Tegra210.

- #address-cells: The number of cells used to represent physical base addresses

  in the aconnect address space. Should be 1.

- #size-cells: The number of cells used to represent the size of an address

  range in the aconnect address space. Should be 1.

- ranges: Mapping of the aconnect address space to the CPU address space.



All devices accessed via the ACONNNECT are described by child-nodes.



Example:



	aconnect@702c0000 {

		compatible = "nvidia,tegra210-aconnect";

		clocks = <&tegra_car TEGRA210_CLK_APE>,

			 <&tegra_car TEGRA210_CLK_APB2APE>;

		clock-names = "ape", "apb2ape";

		power-domains = <&pd_audio>;



		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;





		child1 {

			...

		};



		child2 {

			...

		};

	};

Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml

0 → 100644
+82 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra ACONNECT Bus



description: |

  The Tegra ACONNECT bus is an AXI switch which is used to connnect various

  components inside the Audio Processing Engine (APE). All CPU accesses to

  the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All

  devices accessed via the ACONNNECT are described by child-nodes.



maintainers:

  - Jon Hunter <jonathanh@nvidia.com>



properties:

  compatible:

    oneOf:

      - const: nvidia,tegra210-aconnect

      - items:

          - enum:

              - nvidia,tegra186-aconnect

              - nvidia,tegra194-aconnect

          - const: nvidia,tegra210-aconnect



  clocks:

    items:

      - description: Must contain the entry for APE clock

      - description: Must contain the entry for APE interface clock



  clock-names:

    items:

      - const: ape

      - const: apb2ape



  power-domains:

    maxItems: 1



  "#address-cells":

    const: 1



  "#size-cells":

    const: 1



  ranges: true



patternProperties:

  "@[0-9a-f]+$":

    type: object



required:

  - compatible

  - clocks

  - clock-names

  - power-domains

  - "#address-cells"

  - "#size-cells"

  - ranges



additionalProperties: false



examples:

  - |

    #include<dt-bindings/clock/tegra210-car.h>



    aconnect@702c0000 {

        compatible = "nvidia,tegra210-aconnect";

        clocks = <&tegra_car TEGRA210_CLK_APE>,

                 <&tegra_car TEGRA210_CLK_APB2APE>;

        clock-names = "ape", "apb2ape";

        power-domains = <&pd_audio>;



        #address-cells = <1>;

        #size-cells = <1>;

        ranges = <0x702c0000 0x702c0000 0x00040000>;



        // Child device nodes follow ...

    };



...

Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt

deleted100644 → 0
+0 −56
Original line number Diff line number Diff line 
* NVIDIA Tegra Audio DMA (ADMA) controller



The Tegra Audio DMA controller that is used for transferring data

between system memory and the Audio Processing Engine (APE).



Required properties:

- compatible: Should contain one of the following:

  - "nvidia,tegra210-adma": for Tegra210

  - "nvidia,tegra186-adma": for Tegra186 and Tegra194

- reg: Should contain DMA registers location and length. This should be

  a single entry that includes all of the per-channel registers in one

  contiguous bank.

- interrupts: Should contain all of the per-channel DMA interrupts in

  ascending order with respect to the DMA channel index.

- clocks: Must contain one entry for the ADMA module clock

  (TEGRA210_CLK_D_AUDIO).

- clock-names: Must contain the name "d_audio" for the corresponding

  'clocks' entry.

- #dma-cells : Must be 1. The first cell denotes the receive/transmit

  request number and should be between 1 and the maximum number of

  requests supported. This value corresponds to the RX/TX_REQUEST_SELECT

  fields in the ADMA_CHn_CTRL register.





Example:



adma: dma@702e2000 {

	compatible = "nvidia,tegra210-adma";

	reg = <0x0 0x702e2000 0x0 0x2000>;

	interrupt-parent = <&tegra_agic>;

	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;

	clock-names = "d_audio";

	#dma-cells = <1>;

};

Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml

0 → 100644
+99 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NVIDIA Tegra Audio DMA (ADMA) controller



description: |

  The Tegra Audio DMA controller is used for transferring data

  between system memory and the Audio Processing Engine (APE).



maintainers:

  - Jon Hunter <jonathanh@nvidia.com>



allOf:

  - $ref: "dma-controller.yaml#"



properties:

  compatible:

    oneOf:

      - enum:

          - nvidia,tegra210-adma

          - nvidia,tegra186-adma

      - items:

          - const: nvidia,tegra194-adma

          - const: nvidia,tegra186-adma



  reg:

    maxItems: 1



  interrupts:

    description: |

      Should contain all of the per-channel DMA interrupts in

      ascending order with respect to the DMA channel index.

    minItems: 1

    maxItems: 32



  clocks:

    description: Must contain one entry for the ADMA module clock

    maxItems: 1



  clock-names:

    const: d_audio



  "#dma-cells":

    description: |

      The first cell denotes the receive/transmit request number and

      should be between 1 and the maximum number of requests supported.

      This value corresponds to the RX/TX_REQUEST_SELECT fields in the

      ADMA_CHn_CTRL register.

    const: 1



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include<dt-bindings/clock/tegra210-car.h>



    dma-controller@702e2000 {

        compatible = "nvidia,tegra210-adma";

        reg = <0x702e2000 0x2000>;

        interrupt-parent = <&tegra_agic>;

        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;

        clock-names = "d_audio";

        #dma-cells = <1>;

    };



...