Commit 3d483d57 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvc0: explicitly map PDISP semaphore buffer into each channel's vm 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 9f9f51fc

drivers/gpu/drm/nouveau/nouveau_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -293,6 +293,7 @@ struct nouveau_channel { 


	uint32_t sw_subchannel[8];



	struct nouveau_vma dispc_vma[2];

	struct {

		struct nouveau_gpuobj *vblsem;

		uint32_t vblsem_head;

drivers/gpu/drm/nouveau/nouveau_object.c

+16 −0
Original line number Diff line number Diff line
@@ -717,6 +717,17 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, 
		nv_wo32(chan->ramin, 0x0204, upper_32_bits(vpgd->obj->vinst));

		nv_wo32(chan->ramin, 0x0208, 0xffffffff);

		nv_wo32(chan->ramin, 0x020c, 0x000000ff);



		for (i = 0; i < 2; i++) {

			struct nv50_display_crtc *dispc =

				&nv50_display(dev)->crtc[i];



			ret = nouveau_bo_vma_add(dispc->sem.bo, chan->vm,

						 &chan->dispc_vma[i]);

			if (ret)

				return ret;

		}



		return 0;

	}
@@ -841,9 +852,14 @@ void 
nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)

{

	struct drm_device *dev = chan->dev;

	int i;



	NV_DEBUG(dev, "ch%d\n", chan->id);



	for (i = 0; i < 2; i++) {

		struct nv50_display_crtc *dispc = &nv50_display(dev)->crtc[i];

		nouveau_bo_vma_del(dispc->sem.bo, &chan->dispc_vma[i]);

	}

	nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);

	nouveau_gpuobj_ref(NULL, &chan->vm_pd);

drivers/gpu/drm/nouveau/nv50_display.c

+2 −2
Original line number Diff line number Diff line
@@ -415,8 +415,6 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, 


	/* synchronise with the rendering channel, if necessary */

	if (likely(chan)) {

		u64 offset = dispc->sem.bo->vma.offset + dispc->sem.offset;



		ret = RING_SPACE(chan, 10);

		if (ret) {

			WIND_RING(evo);
@@ -438,6 +436,8 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, 
			else

				OUT_RING  (chan, chan->vram_handle);

		} else {

			u64 offset = chan->dispc_vma[nv_crtc->index].offset;

			offset += dispc->sem.offset;

			BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);

			OUT_RING  (chan, upper_32_bits(offset));

			OUT_RING  (chan, lower_32_bits(offset));