Commit 3d05181a authored by Jin Yao's avatar Jin Yao Committed by Arnaldo Carvalho de Melo
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perf vendor events: Update Skylake client events to v50 



- Update Skylake events to v50.
- Update Skylake JSON metrics from TMAM 4.0.
- Fix the issue in DRAM_Parallel_Reads
- Fix the perf test warning

Before:

  root@kbl-ppc:~# perf stat -M DRAM_Parallel_Reads -- sleep 1
  event syntax error: '{arb/event=0x80,umask=0x2/,arb/event=0x80,umask=0x2,thresh=1/}:W'
                       \___ unknown term 'thresh' for pmu 'uncore_arb'

  valid terms: event,edge,inv,umask,cmask,config,config1,config2,name,period,percore

  Initial error:
  event syntax error: '..umask=0x2/,arb/event=0x80,umask=0x2,thresh=1/}:W'
                                    \___ Cannot find PMU `arb'. Missing kernel support?

  root@kbl-ppc:~# perf test metrics
  10: PMU events                                 :
  10.3: Parsing of PMU event table metrics               : Skip (some metrics failed)
  10.4: Parsing of PMU event table metrics with fake PMUs: Ok
  67: Parse and process metrics                  : Ok

After:

  root@kbl-ppc:~# perf stat -M MEM_Parallel_Reads -- sleep 1

   Performance counter stats for 'system wide':

           4,951,646      arb/event=0x80,umask=0x2/ #    26.30 MEM_Parallel_Reads       (50.04%)
             188,251      arb/event=0x80,umask=0x2,cmask=1/                                     (49.96%)

         1.000867010 seconds time elapsed

  root@kbl-ppc:~# perf test metrics
  10: PMU events                                 :
  10.3: Parsing of PMU event table metrics               : Ok
  10.4: Parsing of PMU event table metrics with fake PMUs: Ok
  67: Parse and process metrics                  : Ok

Signed-off-by: default avatarJin Yao <yao.jin@linux.intel.com>
Tested-by: default avatarNamhyung Kim <namhyung@kernel.org>
Acked-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/lkml/93fae76f-ce2b-ab0b-3ae9-cc9a2b4cbaec@linux.intel.com/


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 60136667

tools/perf/pmu-events/arch/x86/skylake/cache.json

+2049 −2051

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tools/perf/pmu-events/arch/x86/skylake/floating-point.json

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Original line number Diff line number Diff line 
[

    {

        "EventCode": "0xC7",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x4"

    },

    {

        "EventCode": "0xC7",

        "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    },

    {

        "EventCode": "0xC7",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x10"

    },

    {

        "EventCode": "0xC7",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x20"

    },

    {

        "EventCode": "0xC7",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.ANY",

        "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "SampleAfterValue": "100003",

        "UMask": "0x1e"

    },

    {

        "EventCode": "0xC7",

        "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "UMask": "0x20",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1"

    },

    {

        "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "EventCode": "0xCA",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3",

        "UMask": "0x1e",

        "EventName": "FP_ASSIST.ANY",

        "SampleAfterValue": "100003",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "UMask": "0x8"

    }

]
 
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tools/perf/pmu-events/arch/x86/skylake/frontend.json

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tools/perf/pmu-events/arch/x86/skylake/memory.json

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tools/perf/pmu-events/arch/x86/skylake/other.json

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[

    {

        "EventCode": "0x32",

        "BriefDescription": "Number of PREFETCHW instructions executed.",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "SW_PREFETCH_ACCESS.NTA",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x32",

        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of PREFETCHNTA instructions executed.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x8"

    },

    {

        "EventCode": "0x32",

        "BriefDescription": "Number of PREFETCHT0 instructions executed.",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x32",

        "EventName": "SW_PREFETCH_ACCESS.T0",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of PREFETCHT0 instructions executed.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    },

    {

        "EventCode": "0x32",

        "BriefDescription": "Number of hardware interrupts received by the processor.",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "EventName": "SW_PREFETCH_ACCESS.T1_T2",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCB",

        "EventName": "HW_INTERRUPTS.RECEIVED",

        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",

        "SampleAfterValue": "203",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Number of PREFETCHNTA instructions executed.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x32",

        "EventName": "SW_PREFETCH_ACCESS.NTA",

        "SampleAfterValue": "2000003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x32",

        "EventName": "SW_PREFETCH_ACCESS.T1_T2",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of PREFETCHW instructions executed.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x4"

    },

    {

        "PublicDescription": "Counts the number of hardware interruptions received by the processor.",

        "EventCode": "0xCB",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "HW_INTERRUPTS.RECEIVED",

        "SampleAfterValue": "203",

        "BriefDescription": "Number of hardware interrupts received by the processor.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x09",

        "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",

        "SampleAfterValue": "2000003",

        "UMask": "0x1"

    }

]
 
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