Commit 3cd7e415 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: drop unused code around thermal range setting 



Leftover of previous cleanups.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1e1964b7

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

+0 −32
Original line number Diff line number Diff line
@@ -2314,37 +2314,6 @@ static void arcturus_log_thermal_throttling_event(struct smu_context *smu) 
			log_buf);

}



static int arcturus_set_thermal_range(struct smu_context *smu,

				       struct smu_temperature_range range)

{

	struct amdgpu_device *adev = smu->adev;

	int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;

	int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;

	uint32_t val;

	struct smu_table_context *table_context = &smu->smu_table;

	struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;



	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,

			range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);

	high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);



	if (low > high)

		return -EINVAL;



	val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

	val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);



	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);



	return 0;

}



static const struct pptable_funcs arcturus_ppt_funcs = {

	/* translate smu index into arcturus specific index */

	.get_smu_msg_index = arcturus_get_smu_msg_index,
@@ -2427,7 +2396,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = { 
	.set_df_cstate = arcturus_set_df_cstate,

	.allow_xgmi_power_down = arcturus_allow_xgmi_power_down,

	.log_thermal_throttling_event = arcturus_log_thermal_throttling_event,

	.set_thermal_range = arcturus_set_thermal_range,

};



void arcturus_set_ppt_funcs(struct smu_context *smu)

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+0 −2
Original line number Diff line number Diff line
@@ -480,7 +480,6 @@ struct pptable_funcs { 
	int (*set_cpu_power_state)(struct smu_context *smu);

	bool (*is_dpm_running)(struct smu_context *smu);

	int (*tables_init)(struct smu_context *smu, struct smu_table *tables);

	int (*set_thermal_fan_table)(struct smu_context *smu);

	int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);

	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);

	int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
@@ -572,7 +571,6 @@ struct pptable_funcs { 
	int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);

	int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);

	void (*log_thermal_throttling_event)(struct smu_context *smu);

	int (*set_thermal_range)(struct smu_context *smu, struct smu_temperature_range range);

};



typedef enum {

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+0 −32
Original line number Diff line number Diff line
@@ -2340,37 +2340,6 @@ static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu) 
	return navi10_dummy_pstate_control(smu, true);

}



static int navi10_set_thermal_range(struct smu_context *smu,

				       struct smu_temperature_range range)

{

	struct amdgpu_device *adev = smu->adev;

	int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;

	int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;

	uint32_t val;

	struct smu_table_context *table_context = &smu->smu_table;

	struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;



	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,

			range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);

	high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);



	if (low > high)

		return -EINVAL;



	val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

	val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);



	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);



	return 0;

}



static const struct pptable_funcs navi10_ppt_funcs = {

	.tables_init = navi10_tables_init,

	.alloc_dpm_context = navi10_allocate_dpm_context,
@@ -2452,7 +2421,6 @@ static const struct pptable_funcs navi10_ppt_funcs = { 
	.run_btc = navi10_run_btc,

	.disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,

	.set_power_source = smu_v11_0_set_power_source,

	.set_thermal_range = navi10_set_thermal_range,

};



void navi10_set_ppt_funcs(struct smu_context *smu)

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

+0 −32
Original line number Diff line number Diff line
@@ -1818,37 +1818,6 @@ static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 
	return val != 0x0;

}



static int sienna_cichlid_set_thermal_range(struct smu_context *smu,

				       struct smu_temperature_range range)

{

	struct amdgpu_device *adev = smu->adev;

	int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;

	int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;

	uint32_t val;

	struct smu_table_context *table_context = &smu->smu_table;

	struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table;



	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,

			range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);

	high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);



	if (low > high)

		return -EINVAL;



	val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

	val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);



	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);



	return 0;

}



static void sienna_cichlid_dump_pptable(struct smu_context *smu)

{

	struct smu_table_context *table_context = &smu->smu_table;
@@ -2587,7 +2556,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 
	.mode1_reset = smu_v11_0_mode1_reset,

	.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,

	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,

	.set_thermal_range = sienna_cichlid_set_thermal_range,

};



void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)

drivers/gpu/drm/amd/powerplay/smu_internal.h

+0 −2
Original line number Diff line number Diff line
@@ -60,7 +60,6 @@ 
#define smu_populate_umd_state_clk(smu)					smu_ppt_funcs(populate_umd_state_clk, 0, smu)

#define smu_set_default_od8_settings(smu)				smu_ppt_funcs(set_default_od8_settings, 0, smu)

#define smu_tables_init(smu, tab)					smu_ppt_funcs(tables_init, 0, smu, tab)

#define smu_set_thermal_fan_table(smu)					smu_ppt_funcs(set_thermal_fan_table, 0, smu)

#define smu_enable_thermal_alert(smu)					smu_ppt_funcs(enable_thermal_alert, 0, smu)

#define smu_disable_thermal_alert(smu)					smu_ppt_funcs(disable_thermal_alert, 0, smu)

#define smu_smc_read_sensor(smu, sensor, data, size)			smu_ppt_funcs(read_sensor, -EINVAL, smu, sensor, data, size)
@@ -90,7 +89,6 @@ 
#define smu_asic_set_performance_level(smu, level)			smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)

#define smu_dump_pptable(smu)						smu_ppt_funcs(dump_pptable, 0, smu)

#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap)	smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)

#define smu_set_thermal_range(smu, range)				smu_ppt_funcs(set_thermal_range, 0, smu, range)

#define smu_disable_umc_cdr_12gbps_workaround(smu)			smu_ppt_funcs(disable_umc_cdr_12gbps_workaround, 0, smu)

#define smu_set_power_source(smu, power_src)				smu_ppt_funcs(set_power_source, 0, smu, power_src)

#define smu_i2c_eeprom_init(smu, control)				smu_ppt_funcs(i2c_eeprom_init, 0, smu, control)