Commit 3b0898f9 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'ixp4xx-dts-v5.14-1' of... 

Merge tag 'ixp4xx-dts-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt

IXP4xx DTS updates for the v5.14 kernel:
- Add ethernet to the boards
- Add PCI hosts to the boards
- Create an expansion bus around the flash memory
- Add the beeper to NSLU2 completing the NSLU2 DTS

* tag 'ixp4xx-dts-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
  ARM: dts: Fix up the IXP4xx ethernet nodes
  ARM: dts: ixp4xx: Add beeper to the NSLU2
  ARM: dts: ixp4xx: Create a proper expansion bus
  ARM: dts: ixp4xx: Add PCI hosts
  ARM: dts: ixp4xx: Add ethernet

Link: https://lore.kernel.org/r/CACRpkdbmRjGW7vpr7hG+jiRTqNMZAyKZNhtvzj=SqhZmb1+F6A@mail.gmail.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 9321a97c e33f8fd9

arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts

+65 −14
Original line number Diff line number Diff line
@@ -90,15 +90,22 @@ gpio-poweroff { 
		timeout-ms = <5000>;

	};



	/* The first 16MB region on the expansion bus */

	flash@50000000 {

	gpio-beeper {

		compatible = "gpio-beeper";

		gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;

	};



	soc {

		bus@50000000 {

			/* The first 16MB region at CS0 on the expansion bus */

			flash@0 {

				compatible = "intel,ixp4xx-flash", "cfi-flash";

				bank-width = <2>;

				/*

				 * 8 MB of Flash in 0x20000 byte blocks

		 * mapped in at 0x50000000

				 * mapped in at CS0.

				 */

		reg = <0x50000000 0x800000>;

				reg = <0x00000000 0x800000>;



				partitions {

					compatible = "redboot-fis";
@@ -107,3 +114,47 @@ partitions { 
				};

			};

		};



		pci@c0000000 {

			status = "ok";



			/*

			 * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant

			 * We have slots (IDSEL) 1, 2 and 3.

			 */

			interrupt-map =

			/* IDSEL 1 */

			<0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */

			<0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */

			<0x0800 0 0 3 &gpio0 9  3>, /* INT C on slot 1 is irq 9 */

			<0x0800 0 0 4 &gpio0 8  3>, /* INT D on slot 1 is irq 8 */

			/* IDSEL 2 */

			<0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */

			<0x1000 0 0 2 &gpio0 9  3>, /* INT B on slot 2 is irq 9 */

			<0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */

			<0x1000 0 0 4 &gpio0 8  3>, /* INT D on slot 2 is irq 8 */

			/* IDSEL 3 */

			<0x1800 0 0 1 &gpio0 9  3>, /* INT A on slot 3 is irq 9 */

			<0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */

			<0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */

			<0x1800 0 0 4 &gpio0 8  3>; /* INT D on slot 3 is irq 8 */

		};



		ethernet@c8009000 {

			status = "ok";

			queue-rx = <&qmgr 3>;

			queue-txready = <&qmgr 20>;

			phy-mode = "rgmii";

			phy-handle = <&phy1>;



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;



				phy1: ethernet-phy@1 {

					reg = <1>;

				};

			};

		};

	};

};

arch/arm/boot/dts/intel-ixp42x.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -7,6 +7,10 @@ 


/ {

	soc {

		pci@c0000000 {

			compatible = "intel,ixp42x-pci";

		};



		interrupt-controller@c8003000 {

			compatible = "intel,ixp42x-interrupt";

		};

arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts

+91 −13
Original line number Diff line number Diff line
@@ -76,14 +76,16 @@ pld1: pld@57 { 
		};

	};



	flash@50000000 {

	soc {

		bus@50000000 {

			flash@0 {

				compatible = "intel,ixp4xx-flash", "cfi-flash";

				bank-width = <2>;

				/*

				 * 32 MB of Flash in 0x20000 byte blocks

		 * mapped in at 0x50000000

				 * mapped in at CS0.

				 */

		reg = <0x50000000 0x2000000>;

				reg = <0x00000000 0x2000000>;



				partitions {

					compatible = "redboot-fis";
@@ -92,3 +94,79 @@ partitions { 
				};

			};

		};



		pci@c0000000 {

			status = "ok";



			/*

			 * In the boardfile for the Cambria from OpenWRT the interrupts

			 * are assigned one per IDSEL, so all 4 interrupts from IDSEL

			 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2

			 * connected to IRQ 10 etc. I find this highly unlikely so I

			 * have instead assumed that they are rotated (swizzled) like

			 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.

			 */

			interrupt-map =

			/* IDSEL 1 */

			<0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */

			<0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */

			<0x0800 0 0 3 &gpio0 9  3>, /* INT C on slot 1 is irq 9 */

			<0x0800 0 0 4 &gpio0 8  3>, /* INT D on slot 1 is irq 8 */

			/* IDSEL 2 */

			<0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */

			<0x1000 0 0 2 &gpio0 9  3>, /* INT B on slot 2 is irq 9 */

			<0x1000 0 0 3 &gpio0 8  3>, /* INT C on slot 2 is irq 8 */

			<0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */

			/* IDSEL 3 */

			<0x1800 0 0 1 &gpio0 9  3>, /* INT A on slot 3 is irq 9 */

			<0x1800 0 0 2 &gpio0 8  3>, /* INT B on slot 3 is irq 8 */

			<0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */

			<0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */

			/* IDSEL 4 */

			<0x2000 0 0 1 &gpio0 8  3>, /* INT A on slot 3 is irq 8 */

			<0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */

			<0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */

			<0x2000 0 0 4 &gpio0 9  3>, /* INT D on slot 3 is irq 9 */

			/* IDSEL 6 */

			<0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */

			<0x3000 0 0 2 &gpio0 9  3>, /* INT B on slot 3 is irq 9 */

			<0x3000 0 0 3 &gpio0 8  3>, /* INT C on slot 3 is irq 8 */

			<0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */

			/* IDSEL 15 */

			<0x7800 0 0 1 &gpio0 8  3>, /* INT A on slot 3 is irq 8 */

			<0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */

			<0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */

			<0x7800 0 0 4 &gpio0 9  3>; /* INT D on slot 3 is irq 9 */

		};



		ethernet@c800a000 {

			status = "ok";

			queue-rx = <&qmgr 4>;

			queue-txready = <&qmgr 21>;

			phy-mode = "rgmii";

			phy-handle = <&phy1>;



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;



				phy1: ethernet-phy@1 {

					reg = <1>;

				};



				phy2: ethernet-phy@2 {

					reg = <2>;

				};

			};

		};



		ethernet@c800c000 {

			status = "ok";

			queue-rx = <&qmgr 2>;

			queue-txready = <&qmgr 19>;

			phy-mode = "rgmii";

			phy-handle = <&phy2>;

			intel,npe-handle = <&npe 0>;

		};

	};

};

arch/arm/boot/dts/intel-ixp43x.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -8,6 +8,10 @@ 


/ {

	soc {

		pci@c0000000 {

			compatible = "intel,ixp43x-pci";

		};



		interrupt-controller@c8003000 {

			compatible = "intel,ixp43x-interrupt";

		};

arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -30,5 +30,38 @@ i2c@c8011000 { 
			interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";

		};



		/* This is known as EthB1 */

		ethernet@c800d000 {

			compatible = "intel,ixp4xx-ethernet";

			reg = <0xc800d000 0x1000>;

			status = "disabled";

			intel,npe = <1>;

			/* Dummy values that depend on firmware */

			queue-rx = <&qmgr 0>;

			queue-txready = <&qmgr 0>;

		};



		/* This is known as EthB2 */

		ethernet@c800e000 {

			compatible = "intel,ixp4xx-ethernet";

			reg = <0xc800e000 0x1000>;

			status = "disabled";

			intel,npe = <2>;

			/* Dummy values that depend on firmware */

			queue-rx = <&qmgr 0>;

			queue-txready = <&qmgr 0>;

		};



		/* This is known as EthB3 */

		ethernet@c800f000 {

			compatible = "intel,ixp4xx-ethernet";

			reg = <0xc800f000 0x1000>;

			status = "disabled";

			intel,npe = <3>;

			/* Dummy values that depend on firmware */

			queue-rx = <&qmgr 0>;

			queue-txready = <&qmgr 0>;

		};

	};

};