Commit 3ae84d92 authored by Jesse Brandeburg's avatar Jesse Brandeburg Committed by Auke Kok
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ixgb: fix cache miss due to miscalculation 



Reduce writeback threshold by 1. We were instructing the hardware to
wait until the 17th descriptor which went over the cache line limit.

Signed-off-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: default avatarAuke Kok <auke.jan.h.kok@intel.com>
parent 0fe198a5

drivers/net/ixgb/ixgb_main.c

+6 −6
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ module_param(debug, int, 0); 
MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");



/* some defines for controlling descriptor fetches in h/w */

#define RXDCTL_WTHRESH_DEFAULT 16	/* chip writes back at this many or RXT0 */

#define RXDCTL_WTHRESH_DEFAULT 15  /* chip writes back at this many or RXT0 */

#define RXDCTL_PTHRESH_DEFAULT 0   /* chip considers prefech below

                                    * this */

#define RXDCTL_HTHRESH_DEFAULT 0   /* chip will only prefetch if tail